VLSI????

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VLSI????

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• ???????????????????????
• (VLSI Design and Education Center VDEC)
• komatsu_at_cad.t.u-tokyo.ac.jp
• http//www.cad.t.u-tokyo.ac.jp
• 2002?6?6?(?)

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• VLSI????????
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• CAD
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VLSI????????

• VLSI?????????????
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• VLSI????
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• ?????PDS????????
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???????

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• ???????100W????
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???????????? (ITRS1999, 2000Update??,
http//public.itrs.net)
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???????????

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• ?1????????1W???????

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CMOS???????

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????????

• ????CL????????????
• VLSI???????????????

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?????????

• ???????????nMOS, pMOS?????ON????????
• ?Vth???????

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VLSI?????????

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• SOI(Silicon On Insulator)
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VLSI?????????

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????(glitch)???

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MTCMOS (Multithreshold-Voltage CMOS)

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• ????????VDDV, GNDV?????????????
• ????????Vt????????????

S. Mutoh et al., IEEE Journal of Solid State
Circuits, 1995.
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Variable Threshold voltage CMOS (VTCMOS)

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• ?????????Vt
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• Application specific??????

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????????????????????(1)

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????????????????????(2)

• ??????????????????????????????DSP?Video?Audio
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Source Rabaey, Pedram, Low Power Design
Methodologies
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Gated Clock

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?????(??)???????

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??????I/O???????????????????????????????????
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VLSI???????????

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• Application specific ???????????????

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VLSI????????????????

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3??????????????
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?????

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• ??????????????????????????(DSP??)
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?????(2)

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• Instruction?????????
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???????

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  ????????????/???????????
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?????????????(1)

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• Gray???
• ??1????1???????
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?????????????(2)

• T0???
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• ?????1???
• INC or Jump

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???????????????

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• INTEL SpeedStep, Transmeta Crusoe??
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?????CAD??

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• 50???????????????
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Gate-level techniques

• Optimization is carried out in three steps
• Technology independent transformation
• Library binding
• Re-mapping

The synthesis flow must be a tightly coupled
estimation flow
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Technology independent synthesis

• Revised algebraic techniques
• Modification of cost metric

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Example of technology independent synthesis (1)

• f1 is the least switched literal, though literal
  count is the same for all three factorizations.

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Dont care-based optimization

• Boolean optimization is more general and powerful
  than algebraic transformation.
• Optimizing nodes function f may change the
  switching activity at the nodes output.
• This variation propagates to fanout nodes.

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Example of technology independent synthesis (2)

• If the node has a large fanout, its increased
  switching activity cause an increase in the
  global switched-literal metric despite the local
  decrease.
• To address this problem
• Re-compute switching in fanout cones
• Restrict the dont care set available

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Library binding(technology mapping)

• More detailed and accurate power optimization
  than technology independent power optimization
• Partitioned in two contributions
• Internal power (cell power)
• Pdyn, Psc
• External power (node power)
• External Pdyn (driving cells)
• Optimal mapping requires careful balancing of the
  two components, while satisfying side constraints.

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Technology mapping

• Low power library binding produces more reliable
  results
• Accurate power model (gate capacitance, internal
  power)
• 10 to 15 power savings for area-optimized
  circuits
• Power and area reductions are positively
  correlated.

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Example of technology mapping
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Re-mapping transformations

• Applied to gate-level netlist
• Re-mapping transformations are currently the most
  successful power optimizations in commercial
  synthesis tools.
• Back-annotation of wiring capacitance
• Focus on hot spots
• Significant room for improvement
• Re-factoring, polarity assignment, pin swapping
• All techniques are locally applied (single cell
  or a small group of cells)

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Example of re-mapping transformations (1)
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Rewiring method

• Focusing on nets with high switching activity,
  and trying to eliminate them.
• This method is powerful (15 to 20 switching
  reduction), but it has not been implemented in
  commercial tools.

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Path equalization

• Equalize the path lengths in the logic network.
• Reduction of spurious switching
• Applicable for arithmetic circuits

MAC unit of StrongARM Wallace-Tree multiplier
and carry look-ahead adder 23 power
reduction 25 speed up
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Gate resizing

• Synthesized logic has much more irregular
  structure than arithmetic circuit.
• Gates on fast path -gt downsized (lower cap.)
• Gates on slow path -gt enlarged (faster tr. time)
• Reduction of spurious switching
• Trade off between output switching power and
  internal short circuit power.

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• CAD??
• Low Power CAD
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