LCLS LLRF Distributed Control System - PowerPoint PPT Presentation

About This Presentation
Title:

LCLS LLRF Distributed Control System

Description:

LCLS LLRF Distributed Control System Dayle Kotturi Controls Department SLAC National Accelerator Lab – PowerPoint PPT presentation

Number of Views:129
Avg rating:3.0/5.0
Slides: 53
Provided by: apsAnlGov2
Learn more at: https://epics.anl.gov
Category:

less

Transcript and Presenter's Notes

Title: LCLS LLRF Distributed Control System


1
LCLS LLRF Distributed Control System
  • Dayle Kotturi
  • Controls Department
  • SLAC National Accelerator Lab

2
LCLS LLRF Distributed Control System
  • Outline
  • Scope
  • Global Overview
  • General stability requirements
  • Principal motivator
  • Solutions
  • Throughput measurement
  • Conclusions
  • Additional resources

3
Scope
  • The low level RF controls system consists of RF
    phase and amplitude controls at these locations
  • Laser
  • Gun
  • L0-A (a.k.a. L0-1)
  • L0-B (a.k.a. L0-2)
  • L0 Transverse cavity
  • L1-S
  • L1-X
  • L2 using 2 klystrons to control avg phase/ampl
    of L2
  • L3 Transverse cavity
  • L3 - here is a bit different (lots of klystrons!)

4
LLRF Global Overview
5
General stability requirements
  • For LCLS, the general RF stability requirements
    are 0.1 deg phase and 0.1 amplitude in L0 and
    L1 for S band.

6
Principal motivator
  • Placing the digitizers next to the low noise RF
    components eliminates transmission of low noise
    analog signals outside the chassis.

7
(No Transcript)
8
(No Transcript)
9
(No Transcript)
10
(No Transcript)
11
Phase/Amplitude Detector -gt VME
12
OS, BSP and EPICS versions
  • PAD
  • rtems4.9.1
  • m68k uC5282
  • epics-R3.14.10
  • VME
  • rtems4.9.1
  • powerpc beatnik (mvme5500/mvme6100)
  • epics-R3.14.8.2
  • PAC
  • rtems4.9.1
  • m68k uC5282
  • epics-R3.14.10

13
PAD waveform readout
14
PAD IOC Stats
15
VME Feedback Calculation
16
VME IOC Stats
17
PAC waveform control
18
Throughput Time PAD-gtVME-gtPAC
19
Throughput steps PAD-gtVME-gtPAC
Event ( matches diagram) Absolute time after trigger (µsec) Description
- 0.0 Trigger delivered to phase/amplitude detector digitizer (PAD)
1 7.2 ISR signals data ready to wake up DAQ task
2 102.0 Channel0 readout and data processing begins (40 Is and 40 Qs)
3 583.2 Channel1 readout and data processing begins (40 Is and 40 Qs)
4 1041.6 Channel2 readout and data processing begins (40 Is and 40 Qs)
5 1501.6 Channel3 readout and data processing begins (40 Is and 40 Qs)
6 1963.2 PAD starts stream of processed values to VME over private net
7 2349.6 PAD streaming completed. VME parses, does feedback, sends.
8 2508.0 Phase/amplitude controller (PAC) receives new setpts from VME
9 2524.0 PAC writes to FPGA which calcs new WF to send next trigger
10 2529.2 Data is ready
20
Conclusions
  • At 120 Hz operation, time budget8.333 ms
  • LLRF PAD-gtVME-gtPAC throughput measured2.529 ms
    for 4 channels of 40 points each, with no
    offsets,
  • adjust subtract 2.5 µsec per pair of IRQ
    raise/lower calls (8 pairs 20 µsec)
  • adjust one socket sends to multiple PACs add
    switching time

21
Acknowledgements
  • Thanks to Ron Akre and Klystron Department for
    setting up hardware, scopes and signal generators
  • Thanks to SLAC NAL Controls Group

22
Additional Information
  • Details of the PAD-gtVME transfer
  • Details of the VME-gtPAC transfer
  • RF stability measurement
  • PAD
  • PAD Block diagram
  • LCLS LLRF website http//www.slac.stanford.edu/gr
    p/lcls/controls/global/subsystems/llrf

23
Details of the PAD-gtVME transfer
  • http//www.slac.stanford.edu/grp/lcls/controls/glo
    bal/sw/epics/epics20team20meetings/presentations
    /lanIpBasic.pdf
  • Raw ethernet packets with IP and UDP headers.
    Similar to BSD sockets.
  • Solution is for low end CPU on small LAN.
  • Requirement ship 1 KB of data in 200 µsec
  • VME initializes, starts and stops PAD streaming
  • When PAD is streaming, device support for
    waveform on VME parses out the values and uses
    them in the feedback calculations of new
    setpoints.

24
Details of the VME-gtPAC transfer
  • On VME, a subroutine record that has calculated
    new setpoints calls a driver routine that sends
    the values to the PAC via udp socket
  • PAC is has thread waiting to receive packet
  • When packet arrives, it parses out the setpoints
    and puts them into mem mapped FPGA

25
LCLS Jitter Specification for 2 Seconds is 0.14
Amplitude and 0.14 degree Phase
Feedback ON 20 Second Plot shows Phase Jitter
0.043 degrees Amplitude Jitter 0.022
Feedback ON 20 Second Plot shows Phase Jitter
0.043 degrees Amplitude Jitter 0.024
Short Term RF Jitter Specification for L0B are
well Exceeded. This is as good as it gets Dont
tell Physicists or they will expect it. Ron Akre
2007
26
About the PAD
  • CPU is MCF5282 (64MHz)
  • The digitizer used is the Linear Technologies
    LTC2208. It was the first 16 bit digitizer chip
    on the market capable of running at 119MHz, it is
    specified to run up to 130MHz.
  • At SLAC NAL, PAD digitizer used for RF, beam
    position monitors, beam charge monitors and bunch
    length monitors.
  • Pohang Light Source is also using PAD for new RF
    system.

27
Phase/amplitude detector (PAD) Block
Ron Akre
28
(No Transcript)
29
LCLS LLRF Distributed Control System
  • Outline
  • Scope
  • General stability requirements
  • Principal motivator
  • Solutions
  • Throughput measurement
  • Conclusions
  • Additional resources

30
Scope
  • The low level RF controls system consists of RF
    phase and amplitude controls at these locations
  • Laser
  • Gun
  • L0-A (a.k.a. L0-1)
  • L0-B (a.k.a. L0-2)
  • L0 Transverse cavity
  • L1-S
  • L1-X
  • L2 using 2 klystrons to control avg phase/ampl
    of L2
  • L3 Transverse cavity
  • L3 - here is a bit different (lots of klystrons!)

31
General stability requirements
  • For LCLS, the general RF stability requirements
    are 0.1 deg phase and 0.1 amplitude in L0 and
    L1 for S band.

32
Principal motivator
  • Placing the digitizers next to the low noise RF
    components eliminates transmission of low noise
    analog signals outside the chassis.

33
(No Transcript)
34
(No Transcript)
35
(No Transcript)
36
(No Transcript)
37
Phase/Amplitude Detector -gt VME
38
OS, BSP and EPICS versions
  • PAD
  • rtems4.9.1
  • m68k uC5282
  • epics-R3.14.10
  • VME
  • rtems4.9.1
  • powerpc beatnik (mvme5500/mvme6100)
  • epics-R3.14.8.2
  • PAC
  • rtems4.9.1
  • m68k uC5282
  • epics-R3.14.10

39
(No Transcript)
40
(No Transcript)
41
(No Transcript)
42
(No Transcript)
43
Measuring Throughput PAD-gtVME-gtPAC
44
Throughput steps PAD-gtVME-gtPAC
Event ( matches diagram) Absolute time after trigger (µsec) Description
- 0.0 Trigger delivered to phase/amplitude detector digitizer (PAD)
1 7.2 ISR signals data ready to wake up DAQ task
2 102.0 Channel0 readout and data processing begins (40 Is and 40 Qs)
3 583.2 Channel1 readout and data processing begins (40 Is and 40 Qs)
4 1041.6 Channel2 readout and data processing begins (40 Is and 40 Qs)
5 1501.6 Channel3 readout and data processing begins (40 Is and 40 Qs)
6 1963.2 PAD starts stream of processed values to VME over private net
7 2349.6 PAD streaming completed. VME parses, does feedback, sends.
8 2508.0 Phase/amplitude controller (PAC) receives new setpts from VME
9 2524.0 PAC writes to FPGA which calcs new WF to send next trigger
10 2529.2 Data is ready
45
Conclusions
  • At 120 Hz operation, time budget8.333 ms
  • LLRF PAD-gtVME-gtPAC throughput measured2.529 ms
    for 4 channels of 40 points each, with no
    offsets,
  • adjust subtract 2.5 µsec per pair of IRQ
    raise/lower calls (8 pairs 20 µsec)
  • adjust one socket sends to multiple PACs add
    switching time

46
Acknowledgements
  • Thanks as always to Ron Akre and Klystron
    Department for setting up hardware, scopes and
    signal generators
  • Thanks to SLAC NAL Controls Group

47
Additional Information
  • Details of the PAD-gtVME transfer
  • Details of the VME-gtPAC transfer
  • RF stability measurement
  • PAD
  • PAD Block diagram
  • LCLS LLRF website http//www.slac.stanford.edu/gr
    p/lcls/controls/global/subsystems/llrf

48
Details of the PAD-gtVME transfer
  • http//www.slac.stanford.edu/grp/lcls/controls/glo
    bal/sw/epics/epics20team20meetings/presentations
    /lanIpBasic.pdf
  • Raw ethernet packets with IP and UDP headers.
    Similar to BSD sockets.
  • Solution is for low end CPU on small LAN.
  • VME initializes, starts and stops PAD streaming
  • When PAD is streaming, device support for
    waveform on VME parses out the values and uses
    them in the feedback calculations of new
    setpoints.

49
Details of the VME-gtPAC transfer
  • On VME, a subroutine record that has calculated
    new setpoints calls a driver routine that sends
    the values to the PAC via udp socket
  • PAC is has thread waiting to receive packet
  • When packet arrives, it parses out the setpoints
    and puts them into mem mapped FPGA

50
LCLS Jitter Specification for 2 Seconds is 0.14
Amplitude and 0.14 degree Phase
Feedback ON 20 Second Plot shows Phase Jitter
0.043 degrees Amplitude Jitter 0.022
Feedback ON 20 Second Plot shows Phase Jitter
0.043 degrees Amplitude Jitter 0.024
Short Term RF Jitter Specification for L0B are
well Exceeded. This is as good as it gets Dont
tell Physicists or they will expect it. Ron Akre
2007
51
About the PAD
  • The digitizer used is the Linear Technologies
    LTC2208. It was the first 16 bit digitizer chip
    on the market capable of running at 119MHz, it is
    specified to run up to 130MHz.
  • At SLAC NAL, PAD digitizer used for RF, beam
    position monitors, beam charge monitors and bunch
    length monitors.
  • Pohang Light Source is also using PAD for new RF
    system.

52
Phase/amplitude detector (PAD) Block
Ron Akre
Write a Comment
User Comments (0)
About PowerShow.com