Implication Graphs and Logic Testing

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Implication Graphs and Logic Testing

• Vishwani D. Agrawal
• James J. Danaher Professor
• Dept. of ECE, Auburn University
• Auburn, AL 36849
• vagrawal_at_eng.auburn.edu
• www.eng.auburn.edu/vagrawal
• Joint research with M. L. Bushnell, Rutgers
  University, Piscataway, NJ
• K. K. Dave, ATI Research, Yardley, PA

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Implication Graph

• An implication graph (IG) represents the
  implication relations between pairs of Boolean
  variables.

a
b
an implication
contrapositive implication
a
b
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Implication Graph of a Logic Gate
c ab
Boolean false function ab c 0
ac bc abc 0
a
c
b
c
a
b

• Chakradhar et al. -- IEEE-DT, 1990

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Global Implications and Transitive Closure
a
c
b

a
c
b
Transitive closure edge
c
a
b
c 0
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Transitive Closure

• Transitive closure (TC) of a directed graph
  contains the same set of nodes as the original
  graph.
• If there is a directed path from node a to b,
  then the transitive closure contains an edge from
  a to b.

A Graph
Transitive Closure
a
a
b
b
a b c d a 0 1 0 0 b 0 0 1 0 c
0 0 0 1 d 0 0 0 0
a b c d a 0 1 1 1 b 0 0 1 1 c
0 0 0 1 d 0 0 0 0
d
d
c
c
A graph
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Transitive Closure Warshalls Algorithm
procedure Warshall (var A array1n, 1n of
boolean C array1n, 1n of boolean)
Warshall makes A the transitive closure of C
var i, j, k integer begin for i 1
to n do for j 1 to n do Ai, j
Ci, j for k 1 to n do O(n3) for i
1 to n do for j 1 to n do if Ai,
j false then Ai, j Ai, k and Ak,
j end Warshall
S. Warshall, A Theorem on Boolean Matrices, J.
ACM, vol. 9, no. 1, pp. 11-12, 1962. A. V. Aho,
J. E. Hopcroft and J. D. Ullman, Data Structures
and Algorithms, Reading, Massachusetts
Addison-Wesley, 1983, p. 213.
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Transitive Closure Update Algorithm

• Start constructing transitive closure (TC) by
  placing all nodes and no edges. This edge-less
  graph is its own TC.
• Add edges to TC in any arbitrary order
• For each edge i ? j find
• P set of parent nodes of i
• C set of child nodes of j
• Add edges P, i ? C, j

K. Dave, Using Contrapositive Rule to Enhance
the Implication Graphs of Logic Circuits,
Masters Thesis, Rutgers University, Dept. of
ECE, Piscataway, New Jersey, May 2004.
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Update Algorithm
p2
p1
P, i
Edges before i? j is added
i
Edges after i? j is added
j
C, j
c1
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Update Algorithm Example
b
a
a
b
c
d
c
d
A directed graph
a
a
a
b
b
b
c
c
c
d
d
d
Transitive closure
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Logic Testing Stuck-at Fault

• A type of fault, which causes a line to hold a
  constant logic value, irrespective of change of
  state at previous stages.
• There are two types of stuck-at-faults
• Stuck-at-1
• Stuck-at-0
• Detection of a fault requires the fault to be
  activated and its effect observed at a primary
  output (PO).
• Fault a s-a-1 is detectable, if following
  conditions are simultaneously satisfied
• a 0 fault is activated
• Oa 1 observability is true

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Observability Variables

• Observability variable of a signal represents
  whether or not that signal is observable at a PO.
  It can be true or false.

Oa
Oc 1
Oc
a b
Oa
c
b
(PO)
Ob
Agrawal, Bushnell and Lin, Redundancy
Identification using Transitive Closure, Proc.
Asian Test Symp., 1996, pp. 5-9.
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Redundant Faults

• A fault that has no test is called an untestable
  fault.
• Any untestable fault in a combinational circuit
  is a redundant fault because it does not cause
  any change in the input/output logic function of
  the circuit.
• Identification of redundant faults is useful
  because they can be removed
• from testing consideration, or
• from hardware
• Fault a stuck-at-1 is redundant if
• either a 1 no controllability
• or Oa 0 no observability
• or a 0 ? Oa 0 no drivability
• or Oa ? a no drivability

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Limitation of Implication Graph
c
a
b
c
a
d
s-a-0
e
s-a-0
b
d
Circuit with two redundant faults
Implication graph (some nodes and edges not shown)
Implication graph shows no implications of c and
d on their observabilities.
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Adding Partial Implications
c ab
Boolean false function ab c 0
ac bc abc 0
a
c
b
Henftling and Wittmann, AEÜ, 1995 (? node)
?
Dave, Masters Thesis, 2004 (V node)
c
a
b
? and V nodes represent partial implications
V
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Using Partial Implications
c
a
b
c
a
d
s-a-0
e
s-a-0
b
d
Circuit with two redundant faults
Implication graph (some nodes and edges not shown)
Implication Partial implication
Transitive closure edge
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Another Example
s-a-0 s-a-1
a
c
b
s-a-0
e
s-a-0 s-a-1
d
Contrapositive of d ? e
e
a
c
d
b
?1
?2
?3
a
e
c
d
b
e 0
?4
V1
V2
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Results on ISCAS Circuits
Circuit Total faults Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time Redundant faults identified and run time
Circuit Total faults TRAN Chakradhar et al. TRAN Chakradhar et al. FIRE Iyer and Abramovici FIRE Iyer and Abramovici Imp. graph Mehta et al. Imp. graph Mehta et al. Enhanced Imp. Graph Dave et al. Enhanced Imp. Graph Dave et al.
Circuit Total faults Red. faults CPU sa Red. Faults CPU sb Red. Faults CPU sa Red. Faults CPU sa
c1908 1879 7 13.0 6 1.8 2 3.2 5 5.7
c2670 2747 115 95.2 29 1.5 59 4.0 69 6.0
c7552 7550 131 308.0 30 4.7 51 11.5 65 17.7
s1238c 1355 69 17.4 6 1.9 20 2.6 51 5.4
aSun SPARC5 CPU Sec.
bSun SPARC2 CPU Sec.
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Referenced Methods

• TRAN ATPG
• S. T. Chakradhar, V. D. Agrawal and S. G.
  Rothweiler, A Transitive Closure Algorithm for
  Test Generation, IEEE Trans. CAD, vol. 12, no.
  7, pp. 1015-1028, July 1993.
• FIRE Implication analysis
• M. A. Iyer and M. Abramovici, FIRE A
  Fault-Independent Combinational Redundancy
  Identification Algorithm, IEEE Trans. VLSI
  Systems, vol. 4, no. 2, pp. 295-301, June 1996.
• Implication Graph
• V. J. Mehta, Redundancy Identification in Logic
  Circuits using Extended Implication Graph and
  Stem Unobservability Theorems, Masters Thesis,
  Rutgers University, Dept. of ECE, New Brunswick,
  NJ, May 2003.
• K. K. Dave, Using Contrapositive Rule to Enhance
  the Implication Graphs of Logic Circuits,
  Masters Thesis, Rutgers University, Dept. of
  ECE, New Brunswick, NJ, May 2004.

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C1908 Unidentified Redundancies
Redundant faults (s-a-1)
952
949
0/1
0
979
953
887
926
0
74
Total redundant faults 7 identified 5
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C5315 Unidentified Redundancy
Redundant fault (s-a-1)
PI
1
0
0
0/1
0/1
1
1
PI
1
0/1
0/1
PO
0
0
0
1
1
1
1
1
Total redundant faults 59 identified 58
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C5315 Continued . . .
Redundant fault (s-a-1)
PI
1
1
0/1
0/1
0/1
1
1
PI
0
0
0/1
PO
1
1
1
0
1
0
0
1
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Conclusion

• Partial implications improve fault-independent
  redundancy identification present results are
  the best known.
• Transitive closure computation run times are
  empirically linear in the number of nodes for
  benchmark circuits -- the known worst-case
  complexity is O(N3) for N nodes.
• Update algorithm can efficiently compute
  transitive closure when implication graph has
  sparse connectivity.
• Weakness of implication method Observability of
  fanout stems. Recent work has shown that some
  unobservable fanout stems can be identified from
  transitive closure analysis.

Observability of a has no direct relation to
observabilities of b and c, but can be related
to that of d
b
Dominator
Reconvergent gate
a
d
c
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Our Students

• Srimat Chakradhar, NEC
• Qing Lin, Sun Microsystems
• Philip Stanley-Marbell, CMU Graduate Program
• Vivek Gaur, Synopsys
• Vishal Mehta, UCSB PhD Program
• Kunal Dave, ATI