EECS 270 Memories

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EECS 270Memories

• Prof. Igor Markov 2211 EECS
• http//www.eecs.umich.edu/imarkov

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Outline

• Semiconductor memories versus traditional
  sequential circuits
• Types of memories, main characteristics
• RAM and ROM
• Applications
• RAM
• Static
• Dynamic

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EE Times, December 2, 2004

• DRAMs, which account for 5 billionin U.S.
  sales annually, are the most common semiconductor
  memory product. The market is dominated by large
  suppliers such as Infineon, Micron Technology
  Inc., Samsung Electronics Co. Ltd. and Hynix
  Semiconductor Inc.

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Circuits That Remember

• Sequential elements may hold state
• Latches and flip-flops
• Main uses so far
• FSMs and reusable sequential blocks
• Designed for particular applications
• Do not scale very well in terms of design
  (imagine an FSM with 100 FFs)
• Too narrow for general-purpose computing
• Need to store pix, sound, C code, etc

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Large-scale Memories

• De-coupled from combinational logicas much as
  possible
• May still need a few gates for ENABLE, etc
• Simple interface facilitates wider uses
• Interface 1 enumerate all bits
• Write a bit at a given address
• Read a bit at a given address
• Interface 2
• Load or store a bit (no other arguments)
• FIFO or LIFO

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Semiconductor Memories

• Simple interface enablesstuctured, regular
  designs
• Arrays(gates) grids(wires)
• Easy, regular layout
• Wire routing is a solved problem
• Much higher densitiesthan for random logic
• Faster response time
• Easier, cheaper to produce

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Terminology Memory Types

• Read-Only Memory (ROM)
• Much easier to read than to write
• E.g., PROM can be written only once
• Read-Write Memory (RWM) not ROM
• Random Access Memory (RAM)
• Can read/write a bit (or word)with an arbitrary
  address
• Access time independent of address
• Not RAM serial-access memory
• FIFOs, LIFOs, hard drives, magnetic tape

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ROM (e.g., to store serial s)

• Can read bits by address
• Example read(0110) may return 1
• Very similar to combinational logic
• f(0110)1, similar for f(0000), f(0001),
• All arguments/results truth table
• Main difference from comb. logic
• Comb. logic circuits are synthesized
• ROMs are programmed from a data file(e.g., by
  burning small fuses)

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ROM Structure
1 0 0
1 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1
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Commercial ROM Types

• Fixed (written once when produced)
• Mask ROM
• Programmable (written once by user)
• Programmed ROM (PROM)
• Fuses vaporized by high voltage (10-30V)
• Re-programmable (multiple writes)
• Erasable PROM (EPROM) use UV light
• Electrically Erasable PROM (EEPROM),same as
  flash memory

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Volatile Memories

• Volatile memories
• Nothing stored when power is off
• Initialized to 0s when power turned on
• In (CMOS) circuits, logic is implemented using
  electric charges
• Charges dissipate when power is off
• Writeable CMOS memories are volatile
• Main reason for rebooting computers
• ROMs are non-volatile (fuses need no power)

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Non-Volatile RAMs

• Computers need a small amount of non-volatile
  (permanent) writeable memory
• System clock, admin password, etc
• Other BIOS settings
• Volatile memory can be packagedwith a 10-year
  lithium battery
• Very low overall bit density
• MRAM, FeRAM (Motorola, IBM, Infineon)

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Characteristics of RAMs

• Density (bits per square micron)
• Cost (cents/bit still gt than for HDs)
• Read/write latency (access speed, ns)
• Bandwidth (Gbits/s)
• Error-detection and error-correction
• Power consumption (think of laptops)
• The choice of memory type dependson trade-offs
  in applications

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Static vs Dynamic RAM (1)

• Memory cell typically holds 1 bit
• Static RAM (6 tr/cell)
• Each cell has a latch, a NOR, a tri-state gate
• Dynamic RAM (1 tr/cell)
• Each cell has a transistor and a small capacitor
• Much higher density, lower cost
• Problem the capacitor discharges in 10ms
• Solution refresh every bit at a fast rate

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Static vs Dynamic RAM (2)

• DRAM slow, cheaper, denser
• Used in main memory of PCs
• EDO RAM, SDRAM, DDR RAM, RDRAM
• SRAM fast, expensive
• Used in processor caches of PCs
• Cache size significantly affectsthe cost of a
  micro-processor
• Pentium 4 typically has 256KB-1MB cache
• SunUltra-III typically has 8MB cache

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SRAM Interface

• Control signals
• Chip Enable (CE)
• Output Enable (OE)
• Write Enable (OE)
• Outputs are typically connected to busses
• Driven by tri-state gates
• Multiplexed by CE OE

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SRAM Cell

• Uses level-sensitive D-latches,not
  edge-sensitive D FFs
• Fewer transistors per cell, faster signal
  propagation
• When SEL_L is asserted, data?OUTPUT
• When SEL_L WR_L asserted, the latch is open,
  and the IN signal is stored

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SRAM

• OE_L enables reads
• WE_L enables writes
• SEL is provided bydecoder
• IN comes from DIN

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Bidirectional I/O Pins

• of I/O pins is a significant limitation
• Idea multiplex DIN3 and DOUT3 into one pin
• They are never used at the same time
• Same for DIN2 and DOUT2, etc
• Microprocessor buses are also bidirectional

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Dynamic RAM

• 1 transistor 1 capacitor
• Destructive readassert word line
  (select),sense bit line (read)
• Write assert word line, drive bit line
• Refresh cycles needed
• Capacitor discharges (storage decays) in ms
• Internal circuits read word and write back
• One word line selected at a time, readwrite
• All word lines are traversed using a counter
• Refresh cycles initiated regularly by a timer

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DRAM Chip Organization

• Example
• 64Kx1
• Needs 16 address bits
• 8 bits MUXed in 2 steps
• DRAM operation
• More complex thanSRAM operation
• Control signals
• RAS_L (row addr. strobe)
• CAS_L (col. addr. strobe)
• Both rising falling edges are active

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DRAM Charge Leakage

• Typical refresh rate 64 ms for each cell/row
• Typical refresh operation takes lt100ns
• Today (2003) DRAM latency 8ns
• In suspended mode, laptopsuse power mainly for
  DRAM refresh

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Summary

• Memories are reusable sequential blocks
• More scalable/generic than registers counters
• Types of memories main characteristics
• ROM, RAM
• Volatile, static and dynamic
• Density, delay and cost
• On-chip memories
• Mixed with random logic
• Several companies specializein customizable
  memory IP