http://variability.org

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Analysis of ISA and Instruction Sequence
Vulnerability to Dynamic Voltage and Temperature
Variations
Abbas Rahimi, Luca Benini, and Rajesh Gupta
CSE, UC San Diego DEIS, Università di Bologna
http//mesl.ucsd.edu
http//variability.org
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Our Cross-layer Vision
ILV A. Rahimi, L. Benini, R. K. Gupta,
Analysis of Instruction-level Vulnerability to
Dynamic Voltage and Temperature Variations,
DATE, 2012. SLV A. Rahimi, L. Benini, R. K.
Gupta, Application-Adaptive Guardbanding to
Mitigate Static and Dynamic Variability, TC,
2013.
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Agenda

• Dynamic Voltage and Temperature Variation
• Delay Variability Among Pipeline Stages
• Instruction-level Vulnerability (ILV)
• Sequence-level Vulnerability (SLV)
• Classification of Instructions
• Classification of Sequence of Instructions
• Adaptive Guardbanding Utilizing ILV and SLV
• Experimental Results

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Increasing Dynamic Variations

• Increasing dynamic environmental variations in
  ambient condition such as temperature
  fluctuations and supply voltage droops.
• Dynamic Variations contain high-frequency and
  low-frequency components which occur locally as
  well as globally across the die.

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Quantifying Effects of Operating Conditions

• We analyze the effect of a full range of
  operating conditions (a temperature range of
  -40C-125C, and a voltage range of 0.72V-1.1V) on
  the delay and power of LEON ?processor in 65nm
  TSMC.

Critical path (ns)

• Dynamic variations cause the critical path delay
  to increase by a factor of 6.1. Consequently, a
  large conservative guardband into the operating
  frequency is needed to ensure the error-free
  operation in presence of the dynamic variations.

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Delay Variability Among Pipeline Stages
T 125C

• The execute and memory parts are very sensitive
  to voltage and temperature variations, and also
  exhibit a large number of critical paths in
  comparison to the rest of processor.
• Similarly, we anticipate that the instructions
  that significantly exercise the execute and
  memory stages are likely to be more vulnerable to
  voltage and temperature variations?
  Instruction-level Vulnerability (ILV)

VDD 1.1V
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Methodology for ISA-level and Sequence-level
Analysis

• For SPARC V8 instructions (V, T, F) are varied
  and
• ILVi is evaluated for every instructioni with
  random operands
• SLVi is evaluated for a high-frequent sequencei
  of instructions

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ILV and SLV Metadata

• The ILV (SLV) for each instructioni (sequencei)
  at every operating condition is quantified
• where Ni (Mi) is the total number of clock cycles
  in Monte Carlo simulation of instructioni
  (sequencei) with random operands.
• Violationj indicates whether there is a violated
  stage at clock cyclej or not.
• ILVi (SLVi) defines as the total number of
  violated cycles over the total simulated cycles
  for the instructioni (sequencei).

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Classification of Instructions, cont.
ILV at 0.88V, while varying temperature
(V, T) (V, T) (0.88V, -40C) (0.88V, -40C) (0.88V, -40C) (0.88V, -40C) (0.88V, -40C) (0.88V, -40C) (0.88V, 0C) (0.88V, 0C) (0.88V, 0C) (0.88V, 0C) (0.88V, 0C) (0.88V, 125C) (0.88V, 125C) (0.88V, 125C) (0.88V, 125C) (0.88V, 125C) (0.88V, 125C)
Cycle time (ns) Cycle time (ns) 1 1.02 1.06 1.08 1.10 1.12 1 1.02 1.06 1.10 1.12 1.04 1.06 1.08 1.10 1.16 1.18
Logical Arithmetic add 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic and 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic or 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic sll 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic sra 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic srl 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic sub 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic xnor 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Logical Arithmetic xor 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
Mem load 1 0.824 0 0 0 0 1 0.707 0 0 0 1 0.796 0 0 0 0
Mem store 1 0.847 0 0 0 0 1 0.743 0 0 0 1 0.823 0 0 0 0
Mul.Div mul 1 0.996 0.064 0.027 0.017 0 1 0.996 0.065 0.018 0 1 0.876 0.876 0.016 06 0
Mul.Div div 1 0.991 0.989 0.989 0.984 0 1 0.994 0.991 0.973 0 1 0.991 0.991 0.991 0.984 0

• Instructions are partitioned into three main
  classes (i) Logical arithmetic (ii) Memory
  (iii) Multiply divide.
• The 1st class shows an abrupt behavior when the
  clock cycle is slightly varied, mainly because
  the path distribution of the exercised part by
  this class is such that most of the paths have
  the same length, then we have all-or-nothing
  effect, which implies that either all
  instructions within this class fail or all make
  it.

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Classification of Instructions
ILV at 0.72V, while varying temperature
Corners Corners (0.72V, -40C) (0.72V, -40C) (0.72V, -40C) (0.72V, -40C) (0.72V, 0C) (0.72V, 0C) (0.72V, 0C) (0.72V, 0C) (0.72V, 0C) (0.72V, 125C) (0.72V, 125C) (0.72V, 125C) (0.72V, 125C) (0.72V, 125C) (0.72V, 125C) (0.72V, 125C)
Cycle time (ns) Cycle time (ns) 4.10 4.12 4.14 4.16 3.58 3.60 3.62 3.64 3.66 2.88 2.90 2.92 2.94 2.98 3.00 3.20
Logical Arithmetic add 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic and 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic or 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic sll 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic sra 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic srl 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic sub 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic xnor 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Logical Arithmetic xor 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
Mem load 1 0.823 0.823 0 1 0.823 0.823 0 0 1 0.823 0.823 0.823 0.796 0.796 0
Mem store 1 0.847 0.847 0 1 0.847 0.847 0 0 1 0.847 0.847 0.847 0.823 0.823 0
Mul.Div mul 1 0.995 0.995 0 1 0.996 0.994 0 0 1 0.998 0.997 0.996 0.996 0.996 0
Mul.Div div 1 0.995 0.995 0 1 0.995 0.995 0.812 0 1 0.994 0.994 0.993 0.991 0.991 0

• All instruction classes act similarly across the
  wide range of operating conditions as the cycle
  time increases gradually, the ILV becomes 0,
  firstly for the 1st class, then for the 2nd
  class, and finally for the 3rd class.
• For every operating conditions
• ILV (3rd Class) ILV (2nd Class) ILV (1st
  Class)

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Classification of Sequence of Instructions
SLV at (0.81V, 125C)
CT (ns) Seq1 Seq2 Seq3 Seq4 Seq5 Seq6 Seq7 Seq8 Seq9 Seq10 Seq11 Seq12 Seq13 Seq14 Seq15 Seq16 Seq17 Seq18 Seq19 Seq20
1.26 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1.27 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0.690
1.28 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.29 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.30 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.31 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.33 0.878 0.811 0.881 0.880 0.884 0.892 0.877 0.859 0.879 0.758 0.883 0.883 0.811 0.811 0.811 0.952 0.811 0.805 0.810 0
1.34 0.366 0.811 0.515 0.512 0.393 0.429 01 0.859 03 01 0.403 0.407 0.811 0.811 0.811 0.811 0.811 0.805 0.810 0
1.35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

• The top 20 high-frequent sequences (Seq1-Seq20)
  are extracted from 80 Billion dynamic
  instructions of 32 benchmarks.
• Sequences are classified into two classes based
  on their similarities in SLV values
• Class I (Seq1-Seq19) is a mixture of all types of
  instructions including the memory,
  arithmetic/logical, and control instructions.
• Class II (Seq20) only consists of the
  arithmetic/logical instructions.

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Classification of Sequence of Instructions
(V,T) (0.81V, 125C) (V,T) (0.81V, 125C) (V,T) (0.81V, 125C) (V,T) (0.72V, 125C) (V,T) (0.72V, 125C) (V,T) (0.72V, 125C)
CT (ns) Class I Class II CT (ns) Class I Class II
1.26 1 1 1.78 1 1
1.27 1 0.69 1.79 1 0.58
1.28 1 0 1.80 1 0
1.29 1 0 1.81 1 0
1.30 1 0 1.82 1 0
1.31 1 0 1.83 1 0
1.32 1 0 1.84 0.81 0
1.33 0.81 0 1.85 0.13 0
1.34 0.81 0 1.86 0 0
1.35 0 0 1.87 0 0
For every operating conditions SLV (Class I)
SLV (Class II)

• The sequence classification is consistent across
  operating corners.
• SLV value of two classes of the sequences at the
  same corner and with the same cycle time is not
  equal.
• Sequences in Class I need higher guardbands
  compared to Class II, because in addition of
  ALU's critical paths, the critical paths of
  memory are activated (for the load/store
  instructions) as well as the critical paths of
  integer code conditions (for the control
  instructions).

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ILV and SLV? ?

• For every operating conditions
• ILV (3rd Class) ILV (2nd Class) ILV (1st
  Class)
• SLV (Class I) SLV (Class II)

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Adaptive Guardbanding Utilizing ILV and SLV

• We define an adaptive clock scaling for each
  class of instructions/ sequences to mitigate the
  conservative inter- and intra-corner
  guardbanding.
• At the runtime, in every cycle, the PLUT module
  sends the desired frequency to the adaptive
  clocking circuit utilizing the characterized SLV
  metadata of the current sequence and the
  operating condition monitored by CPM.

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Effectiveness of Adaptive Guardbanding

• Full layout results on 45nm TSMC technology
  confirms
• For the intolerant applications, in comparison to
  the worst-case design, the adaptive guardbanding
  eliminates the inter-corner guardbanding by up to
  40 for sequences of Class II, and 37 for
  sequences of Class I.
• Simultaneously, it reduces intra-corner
  guardbanding among the two classes of the
  sequences by up to 5.
• It achieves up to 87 performance improvement for
  error-tolerant (probabilistic) applications in
  comparison to the traditional worst-case design.
• It incurs only 0.022, 0.012, and 0.034
  overheads for the total area, leakage power, and
  total power respectively.

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Conclusion

• The notion of ILV and SLV to dynamic voltage and
  temperature variations is defined.
• Based on that, ISA partitioned into three
  classes
• (i) ALU, (ii) MEMORY, (iii) MULTPLY DIVIDE
• Sequence of instructions are partitioned into two
  classes
• (i) a mixture of all types including ALU, MEM,
  CONTROL, etc.
• (ii) only ALU type instructions
• Leveraging these classifications across adaptive
  guardbanding techniques enables up to 40 speedup
  for error-intolerant (traditional) applications
  and 87 speedup for error-tolerant
  (probabilistic) application, in 45nm TSMC
  technology.

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Thank you!
http//mesl.ucsd.edu
http//variability.org
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Classification of Sequence of Instructions
SLV at (0.81V, -40C).
CT (ns) Seq1 Seq2 Seq3 Seq4 Seq5 Seq6 Seq7 Seq8 Seq9 Seq10 Seq11 Seq12 Seq13 Seq14 Seq15 Seq16 Seq17 Seq18 Seq19 Seq20
1.36 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0.475
1.37 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.38 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.39 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.40 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.41 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1.42 0.878 0.811 0.881 0.880 0.884 0.892 0.877 0.859 0.988 0.758 0.882 0.883 0.811 0.811 0.815 0.870 0.811 0.807 0.810 0
1.43 01 01 0.479 0.396 06 04 01 01 0.901 01 01 01 0.811 0.811 0.811 0.811 0.810 0.805 0.131 0
1.44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0