Processor Basic steps to process an instruction

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Processor Basic steps to process an instruction
IF
ID/OF
EX
MEM
WB
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Datapath
NPC
A? RegIR 6..10 B? RegIR 11..15 Imm?
((IR16)16 IR 11..15
IR ? MemPC NPC ? PC 4
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Datapath (Arith/Logic Inst.)
ALUoutput ? A op B ALUoutput ? A op Imm
A? RegIR 6..10 B? RegIR 11..15 Imm?
((IR16)16 IR 11..15
IR ? MemPC NPC ? PC 4
RegIR16..20 ? ALUoutput
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Datapath (Load Inst.)
ALUoutput ? A op Imm
A? RegIR 6..10 B? RegIR 11..15 Imm?
((IR16)16 IR 11..15
IR ? MemPC NPC ? PC 4
RegIR11-15 ? LMD
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Datapath (Store Inst.)
ALUoutput ? A op Imm
A? RegIR 6..10 B? RegIR 11..15 Imm?
((IR16)16 IR 11..15
IR ? MemPC NPC ? PC 4
MemALUoutput ? B
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Datapath (Branch Inst.)
ALUoutput ? (PC4) op Imm
A? RegIR 6..10 B? RegIR 11..15 Imm?
((IR16)16 IR 11..15
IR ? MemPC NPC ? PC 4
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Instructions of a program
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Time (clock cycles)
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Instructions of a program
1
2
3
4
5
6
7
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CLOCK CYCLE
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Pipelining Lessons

• Pipelining doesnt help latency of single task,
  it helps throughput of entire workload
• Pipeline rate limited by slowest pipeline stage
• Multiple tasks operating simultaneously
• Potential speedup Number pipe stages
• Unbalanced lengths of pipe stages reduces speedup
• Time to fill pipeline and time to drain it
  reduces speedup

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Datapath w/ pipeline
IF
ID
EX
MEM
WB
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Datapath w/ pipeline
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Pipeline
IF
1
2
3
4
INSTRUCTIONS
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6
7
8
9
1
2
3
4
5
6
7
8
9
CLOCK CYCLE
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Pipeline Hazards

• Structural Hazards
• two or more instructions use same hardware at the
  same time.
• Data Hazards
• Data dependencies
• Result from inst. j is needed by inst. k
• Control Hazards
• Branch changes flow, what happen with the
  following instruction(s)

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Resources
Mem (IM)
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Data Hazards
Mem (IM)
R1 R2R3
R5 R1R3
R8 R1-R6
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Data Forwarding
Mem (IM)
R1 R2R3
R5 R1R3
R8 R1-R6
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Datapath w/ pipeline
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Example
ADD R1,R2,R3
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Example
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Example
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Data Hazard Classification
j R1 ? k RY ? R1

• RAW (Read After Write)
• w/ forward only load presents a problem
• WAW
• WAR
• RAR

j R1 ? k R1 ?
j ? R1 k R1 ?
j ? R1 k ? R1
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Data Forwarding (load)
Mem (IM)
R1 LDMem
R5 R1R3
R8 R1-R6
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Data hazard (load)
R1
IF
LW R1,0(R1)
SUB R4,R1,R5
AND R6,R1,R7
OR R8,R1,R9
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Branch
BR R1, LABEL_A
ADD R2,R3,R7
AND R5,R7,R11

LD R4,R2,005
LABEL_A
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Branch
Mem (IM)
BR R1, LABEL_A
ADD R2,R3,R7
AND R5,R7,R11
LD R4,R2,005
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Datapath w/ pipeline
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What to do w/ branch

• Reduce the number of cycles to decide on a
  branch.
• Delayed branch (Software Solutions)
• NO-OP
• move instructions
• from before
• from target
• from fall through

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Branch
Mem (IM)
BR R1, LABEL_A
ADD R2,R3,R7
LD R4,R2,005
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NO-OP
Branch
NO-OP
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From Before
Branch
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From Target
Branch
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From Fall Through
Branch
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Multicycle Operations
I F
I D
MEM
W B
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FP operations

• FP Add 4 cycles
• FP Multiply 7 cycles
• FP Divide 25 cycles

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Example
1 IF
2 ID IF
3 m1 ID IF
4 m2 a1 ID IF
5 m3 a2 X ID
6 m4 a3 M X
7 m5 a4 W M
8 m6 M W
9 m7 W
10 M
11 W
MULTD ADDD LD SD
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MIPS R4000(Superpipelining)
DF Data fetch First half DS Data fetch
Second half TC Tag Check WB Write Back
IF Instruction fetch First half IS
Instruction fetch Second half RF Inst. Decode
Register Fetch EX Execution
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Load
CC1
CC2
CC3
CC4
CC5
CC6
CC7
LW R1
instruction memory
data memory
Reg
Reg
instruction memory
data memory
Reg
Reg
Instruction 1
instruction memory
data memory
Reg
Reg
Instruction 2
instruction memory
data memory
Reg
ADD R2,R1
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Branch
BEQZ
instruction memory
data memory
Reg
Reg
instruction memory
data memory
Reg
Reg
instruction memory
data memory
Reg
Reg
instruction memory
data memory
Reg
instruction memory
data memory
Reg
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Branch (taken)
Branch inst IF IS RF EX DF DS TC WB Delay slot
IF IS RF EX DF DS TC WB stall S S S S S S S S st
all S S S S S S S S Branch target
IF IS RF EX DF DS TC WB
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Branch (not taken)
Branch inst IF IS RF EX DF DS TC WB Delay slot
IF IS RF EX DF DS TC WB Branch inst2 IF IS RF E
X DF DS TC WB Branch inst3 IF IS RF EX DF DS T
C WB Branch inst4 IF IS RF EX DF DS TC WB
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