Datapaths

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Datapaths

• Lecture L10.2
• Sections 10.2, 10.3

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ALU (Sect. 7.5 and Lab 6)
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An ALU datapath
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simple.abl
MODULE simple TITLE 'A simple computer' DECLARATI
ONS hex7seg interface(D3..D0 -gt
a,b,c,d,e,f,g) d7L FUNCTIONAL_BLOCK
hex7seg d7R FUNCTIONAL_BLOCK hex7seg alu
interface(A3..A0,B3..B0, s2..s0 -gt
Y3..Y0,CF,OVF,ZF,NF) alu1
FUNCTIONAL_BLOCK alu reg4bit interface(D3..D0,
clr,clk,load -gt Q3..Q0) W FUNCTIONAL_BLOCK
reg4bit status FUNCTIONAL_BLOCK reg4bit
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simple.abl (cont.)
" INPUT PINS " clk PIN 74 " clock clr PIN
70 " clear PA3..PA0 PIN 11,7,6,5 " Left
Switches S6 - 1..4 PA PA3..PA0
alusel2..alusel0 PIN 3,2,1 " alu
select S7 24 alusel alusel2..alusel0
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simple.abl (cont.)
" OUTPUT PINS " N, Z, V, C PIN 35,36,37,39
ISTYPE 'com' " flags
PW3..PW0 NODE ISTYPE 'reg' "
4-bit reg output PW PW3..PW0
LD3..LD0 PIN 40,41,43,44 ISTYPE 'reg' "
leds 13-16 LD LD3..LD0
a,b,c,d,e,f,g PIN 57,58,61,62,63,65,66 ISTYPE
'com' "Leftmost (tens) 7-segment LED
display aa,bb,cc,dd,ee,ff,gg PIN
15,18,23,21,19,14,17 ISTYPE 'com' "
Rightmost (units) 7-segment LED display
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simple.abl (cont.)
EQUATIONS W.load 1 W.clr clr W.clk
clk W.D3..D0 alu1.Y3..Y0 status.load
1 status.clr clr status.clk clk status.D0
alu1.CF status.D1 alu1.OVF status.D2
alu1.ZF status.D3 alu1.NF alu1.A3..A0
PA alu1.B3..B0 W.Q3..Q0 alu1.s2..s0
alusel2..alusel0
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simple.abl (cont.)
C status.Q0 V status.Q1 Z status.Q2 N
status.Q3 PW W.Q3..Q0 LD
alu1.Y3..Y0 a,b,c,d,e,f,g
d7L.a,b,c,d,e,f,g d7L.D3..D0
PA aa,bb,cc,dd,ee,ff,gg d7R.a,b,c,d,e,f,g
d7R.D3..D0 PW
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simple.abl (cont.)
_at_ radix 16 test_vectors(clk,alusel,PA -gt
PW,C,Z) .C.,0,7 -gt 7,0,0 .C.,1,5 -gt
0C,0,0 .C.,1,6 -gt 2,1,0 .C.,2,9 -gt
7,0,0 .C.,3,1 -gt 6,0,0 .C.,4,0A -gt
5,0,0 .C.,5,0C -gt 4,0,0 .C.,6,2 -gt
6,0,0 .C.,7,0C -gt 0A,0,0 .C.,1,6 -gt
0,1,1 END simple
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A modified datapath
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A datapath with two data registers
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Switching using a demultiplexer
Is it necessary?
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Multiple inputs without multiplexers a design
hazard
0
1
Smoke!
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An optimum datapath
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Datapath of a PIC type processor