Chapter 8 Register Transfers and Datapaths

1
Chapter 8 Register Transfers and Datapaths
2
Introduction

• A datapath consists of processing logic and a
  collection of registers that performs data
  processing.
• A control unit is made up of logic that
  determines the sequence of data-processing
  operations performed by the datapath.

3
Register Transfer Level (RTL) Notation

• A digital system is represented at the register
  transfer level (RTL) when it is specified by the
  following three components
• The set of registers in the system.
• The operations that are performed on the data
  stored in the registers.
• The control that supervises the sequence of
  operations in the system.
• Information transfer from one register to another
• R2 ?? R1

4
RTL Notations (Cont.)

• Conditional statement
• If (T1 1) then (R2 ? R1)
• If (T3 1) then (R2 ? R1, R1 ? R2)
• Other examples of register transfers are as
  follows
• R2 ? R1 R2
• R3 ? R1 1 Increment R3 by 1 (Count up)
• R4 ? shr R4
• R5 ? 0
• The addition is done with a binary parallel
  adder, the incrementing with a counter, and the
  shift with a shift register.

5
Type of Operations

• Transfer operation that transfer data from one
  register to another.
• Arithmetic operations that perform arithmetic on
  data in registers.
• Logic operations that perform bit manipulation of
  non-numeric data in registers.
• Shift operations that shift data in registers.

6
Microoperations

• A register has the capability to perform one or
  more elementary operations such as load, count,
  add, subtract, and shift.
• The elementary operations performed on the data
  stored in registers are called microoperations.
• Load the contents of one register to another.
• Add the contents of two registers and increment
  the content of a register.
• A microoperation is usually, but not always,
  performed in parallel on a string of bits during
  one clock cycle.

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Datapath

• Arithmetic/logic unit (ALU)
• To perform a microoperation, the contents of
  specified source registers are applied to the
  inputs of the shared ALU.
• The combination of a set of registers with a
  shared ALU and interconnecting paths is the
  datapath for the system.
• The datapath and the control unit are the two
  parts of the processor, or CPU, of a computer.

8
Add and Subtract Microoperation
9
Block Diagram of a Datapath
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Arithmetic/Logic Unit

• The ALU is a combinational circuit that performs
  a set of basic arithmetic and logic
  microoperations.
• The ALU has a number of selection lines used to
  determine the operation to be performed.

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Arithmetic Circuit
12
Function Table for Arithmetic Circuit

• Table 7-7

13
Logic Diagram of a 4-Bit Arithmetic Circuit
14
Logic Circuit
15
Arithmetic/Logic Unit
16
4-Bit Basic Shifter
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Barrel Shifter
18
Datapath Representation
19
FS Codes
20
Datapath with Control Variables
21
Encoding of Control Word of the Datapath
22
Examples of Microoperations
23
Example of Microoperations (Cont.)
24
Simulation Results
25
Simulation Results (Cont.)
26
Pipelined Datapath
27
Assembly Line Analogy to Datapath Pipeline
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Block Diagram of Pipelined Datapath
29
Pipeline Execution Pattern
30
Control and Datapath Interaction
31
Algorithmic State Machine (ASM)

• ASM chart is composed of three basic elements
  the state box, the decision box, and the
  conditional box.

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State Box
33
Decision Box

• The decision box describes the effect of an input
  on the control subsystem.

34
Conditional Box
35
ASM Block

• Each block in the ASM chart describes the state
  of the system during one clock-pulse interval.
• The operations within the state and conditional
  boxes are executed with a common clock pulse
  while the system is in state T1.

36
State Diagram
37
Timing Consideration
38
ASM Chart
39
Timing Sequence

• Every block in an ASM chart specifies the
  operations that are to be performed during one
  common clock pulse.
• The operations specified within the state and
  conditional boxes in the block are performed in
  the datapath subsection.
• The change from one state to the next is
  performed in the control logic.

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Timing Sequence (Cont.)
41
Datapath Design

• The requirements for the design of the datapath
  are specified inside the state and conditional
  boxes.
• The control logic is determined from the decision
  boxes and the required state transitions.

42
Datapath for Design Example
43
Register Transfer Representation

• A digital system is represented in the register
  transfer level by specifying the registers in the
  system, the operation performed, and the control
  sequence.

44
RTL Description of Design Example
45
State Table

• DG1 T1A3A4, DG0 T0S T1
• T0 G0
• T1 G1G0
• T2 G1

46
Logic Diagram of Control
47
RTL Description

• //RTL description of design example (Fig.8-9)
• module Example_RTL (S,CLK,Clr,E,F,A)
• //Specify inputs and outputs
• //See block diagram Fig. 8-10
• input S,CLK,Clr
• output E,F
• output 41 A
• //Specify system registers
• reg 41 A //A register
• reg E, F //E and F
  flip-flops
• reg 10 pstate, nstate //control register
• //Encode the states
• parameter T0 2'b00, T1 2'b01, T2 2'b11

48
RTL Description (Cont.)

• //State transition for control logic
• //See state diagram Fig. 8-11(a)
• always _at_(posedge CLK or negedge Clr)
• if (Clr) pstate T0 //Initial state
• else pstate lt nstate //Clocked
  operations
• always _at_ (S or A or pstate)
• case (pstate)
• T0 if(S) nstate T1
• T1 if(A3 A4) nstate T2
• T2 nstate T0
• default nstate T0
• endcase

49
RTL Transfer (Cont.)

• //Register transfer operations
• //See list of operations Fig.8-11(b)
• always _at_(posedge CLK)
• case (pstate)
• T0 if(S)
• begin
• A lt 4'b0000
• F lt 1'b0
• end
• T1
• begin
• A lt A 1'b1
• if (A3) E lt 1'b1
• else E lt 1'b0
• end
• T2 F lt 1'b1
• endcase
• endmodule

50
Binary Multiplier
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ASM Chart
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Control Logic
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Control Block Diagram
54
Sequence and Decoder
DG1 T1 T2 T3Z DG0 T0S T2
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Logic Diagram of Control Unit
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One Flip-Glop per State

• DT0 T0S T3Z
• DT1 T0S
• DT2 T1 T3Z
• DT3 T2

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HDL Description

• module mltp(S,CLK,Clr,Binput,Qinput,C,A,Q,P)
• input S,CLK,Clr
• input 40 Binput,Qinput //Data
  inputs
• output C
• output 40 A,Q
• output 20 P
• //System registers
• reg C
• reg 40 A,Q,B
• reg 20 P
• reg 10 pstate, nstate //control
  register
• parameter T02'b00, T12'b01, T22'b10,
  T32'b11
• //Combinational circuit
• wire Z
• assign Z P //Check
  for zero

58
HDL Description (Cont.)

• //State transition for control
• //See state diagram Fig. 8-15(a)
• always _at_(negedge CLK or negedge Clr)
• if (Clr) pstate T0
• else pstate lt nstate
• always _at_(S or Z or pstate)
• case (pstate)
• T0 if (S) nstate T1
• T1 nstate T2
• T2 nstate T3
• T3 if (Z) nstate T0
• else nstate T2
• endcase

59
HDL Description (Cont.)

• always _at_(negedge CLK)
• case (pstate)
• T0 B lt Binput //Input
  multiplicand
• T1 begin
• A lt 5'b00000
• C lt 1'b0
• P lt 3'b101
  //Initialize counter to n5
• Q lt Qinput //Input
  multiplier
• end
• T2 begin
• P lt P - 3'b001
  //Decrement counter
• if (Q0)
• C,A lt A B //Add
  multiplicand
• end
• T3 begin
• C lt 1'b0 //Clear C
• A lt C,A41 //Shift
  right A
• Q lt A0,Q41 //Shift
  right Q
• end