Title: ECE 875: Electronic Devices
1ECE 875Electronic Devices
- Prof. Virginia Ayres
- Electrical Computer Engineering
- Michigan State University
- ayresv_at_msu.edu
2Lecture 18, 19 Feb 14
Chp. 02 pn junction C-V curves About Pr.
2.02 Mixed linearly graded and abrupt pn
junction About Pr. 2.03 More about the Debye
length
VM Ayres, ECE875, S14
3VM Ayres, ECE875, S14
4Epitaxial layer layer grown in front n-layer
grown on the p substrate formed IN an n-type
epitaxial layer
As grown n-type epitaxial layer
p substrate
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5depletion capacitance .formed IN an n-type
epitaxial layer means formation of a depletion
region WD WDp WDn
As grown n-type epitaxial layer
p substrate
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WDn ?
WDp 0.07 mm
6Find the thickness of the depletion region WDn
formed in the n-type epitaxial layer
As grown n-type epitaxial layer
p substrate
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WDn ?
WDp 0.07 mm
7Find the thickness of the depletion region WDn
formed in the n-type epitaxial layer Under which
bias condition?
Vext
Reverse -1 V
As grown n-type epitaxial layer
p substrate
Equilibrium 0 V
Forward 0.95 V
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WDn ?
WDp 0.07 mm
8Find the thickness of the depletion region WDn
formed in the n-type epitaxial layer Under bias
condition Vrev -1 V, for which WD is biggest.
Given WDp-max 0.07 mm. Find WDn-max
Vext
Reverse -1 V
As grown n-type epitaxial layer
p substrate
Equilibrium 0 V
Forward 0.95 V
VM Ayres, ECE875, S14
WDn ?
WDp 0.07 mm
9Two ways to finish use Method 01
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10Use intercepti
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11Use slope
VM Ayres, ECE875, S14
12Watch out for Units
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13VM Ayres, ECE875, S14
14Lecture 18, 19 Feb 14
Chp. 02 pn junction C-V curves About Pr.
2.02 Mixed linearly graded and abrupt pn
junction About Pr. 2.03 More about the Debye
length
VM Ayres, ECE875, S14
15VM Ayres, ECE875, S14
16For mixed type pn doping, find WD ybi E
max NA-(x) and ND(x) E (x)
VM Ayres, ECE875, S14
17For mixed type pn doping, find WD ybi E
max NA-(x) and ND(x) E (x)
2nd easiest to find
Easiest to find
VM Ayres, ECE875, S14
18D
D
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19Find E max as if
Solve for E m
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20Next step
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21Relation of E max to WDn as if
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Use E m. Solve for WDn
22For mixed type pn doping, find WD ybi E
max NA-(x) and ND(x) E (x)
?
2nd easiest to find
Easiest to find
?
VM Ayres, ECE875, S14
23For mixed type pn doping, find WD ybi E
max NA-(x) and ND(x) E (x)
Find potential drop on p-side using correct
yi(x) formula for linearly graded Find potential
drop on n-side using correct yi(x) formula for
linearly graded ybi potential drop on p-side
potential drop on n-side
?
?
VM Ayres, ECE875, S14
24For mixed type pn doping, find WD ybi E
max NA-(x) and ND(x) E (x)
?
?
?
What do you expect the E (x) plot to look like?
VM Ayres, ECE875, S14
25VM Ayres, ECE875, S14
26For mixed type pn doping, find WD ybi E
max NA-(x) and ND(x) E (x)
?
?
?
What do you expect the doping(x) plot to look
like?
VM Ayres, ECE875, S14
27VM Ayres, ECE875, S14
28Lecture 18, 19 Feb 14
Chp. 02 pn junction C-V curves About Pr.
2.02 Mixed linearly graded and abrupt pn
junction About Pr. 2.03 More about the Debye
length
VM Ayres, ECE875, S14
29Debye length pn example on spring 2012 Midterm
VM Ayres, ECE875, S14
30Debye length pn example on spring 2012 Midterm
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
VM Ayres, ECE875, S14
31Debye length pn example on spring 2012 Midterm
LD 41.2 nm
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
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32Debye length LD ? pos-neg shielding length
Debye shielding
LD 41.2 nm
NA-
ND
NA-
ND
NA-
ND
NA-
ND
NA-
ND
VM Ayres, ECE875, S14
33In Sze abrupt pn junction calculations for E (x)
and yi(x)
r ? Q/WDn Area ND Single type of charge.
This is outside LD.
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
NA-
ND
ND
ND
NA-
NA-
NA-
NA-
NA-
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34Will see Debye shielding length LD again
Chp. 03 metal-semiconductor interface develops
special charge layer to achieve shielding Chp.
04 Chp. 06 metal-insulator-semiconductor
interface develops inversion layer (gate/channel
region in a transistor) during operation
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35Will see Debye shielding length LD again
Chp. 04, Fig. 4
Inversion region e-s ? surface charge Qs formed
in a p-side
VM Ayres, ECE875, S14
36Will see Debye shielding length LD again Chp.
04, fig.4
Where
VM Ayres, ECE875, S14