DSP Builder ????;????;????;???;?????

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?????

• ????
• DSP Builder ????????????????????
• ????
• DSP Builder ???????Simulink??????MATLAB?????DSP
  Builder????,?????????????????????????

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??(1)

• ???? DSP Builder??
• DSP Builder??
• DSP Builder??
• DSP Builder????
• DSP Builder????
• ??

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??(2)

• ???? Altera DSP Builder???
• AltLab?
• ???
• ?????
• ??????
• Rate Change???
• ??????
• ???(Storage)???
• MegaCore????
• ???

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Implementing DSP Designs in FPGA

• Overview

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The Programmable Solutions Company
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Agenda

• Overview
• Designing with DSP Builder Library Blocks
• Simulating Debugging with DSP Builder
• Intellectual Property (IP) Implementation
• FIR, NCO and FFT IP Functions
• Appendix
• Introduction to Altera Devices
• Hardware Acceleration Using Nios II

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What Is a DSP Processor?

• Microprocessor With Specialized Instructions
  Hardware for DSP Applications
• Optimized For High-Performance, Repetitive and
  Numerically Intensive Tasks
• Hardware
• Fixed Floating Point Multipliers
• Co-Processors
• Special Memory Structures
• Multiple Access Memories For Faster Computations
• Run Arithmetic Calculations Faster than General
  Processors

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What Is an FPGA?

• Field Programmable Gate Array
• Device that Has a Regular Architecture (Set of
  Blocks) that Can Be Programmed for Various
  Functions
• Glue Logic
• Customizable Hardware Solution
• Configurable Processors

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DSP Processors vs. FPGAs
High Speed DSP Processor
High Level of Parallel Processing in FPGA

• 1-8 Multipliers
• Needs looping for more than 8 multiplications
• Needs multiple clock cycles because of serial
  computation
• 200 Tap FIR Filter would need 25 clock cycles
  per sample with an 8 MAC unit processor

• Can implement hundreds of MAC functions in an
  FPGA
• Parallel implementation allows for faster
  throughput
• 200 Tap FIR Filter would need 1 clock cycle per
  sample

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Extending Range of Altera Reconfigurable DSP
Solutions
New!
600 -
Performance (MMACs/sec)
100 -
Complete Hardware Implementation
Embedded Processors
Embedded Processors Hardware Acceleration
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FPGA / DSP Challenges

• Designing With FPGAs Is Different!!
• Different Set of Tools
• C-Code vs. VHDL / Verilog
• System-Level Development Verification
• Software/Hardware Co-Development
• Software Design Optimization

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Addressing Challenges

• 1) System-level Development Verification
• DSP Builder Tool
• System Integration
• Bit-true Cycle Accurate Models
• Automatic Translation into Hardware
• 2) Hardware/Software Integration
• SOPC Builder Tool Nios II Processor
• 3) Design Optimization
• Hardware Acceleration
• Flexibility in System Partitioning

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Implementing DSP Designs in FPGAs

• Matlab Simulink
• Overview

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The Mathworks

• Headquarters in Natick, near Boston
• Founded in 1984, Privately Held
• Over 1000 employees
• Direct Offices in UK, France, Italy, Germany,
  Switzerland, Spain, Benelux
• Distributors in 20 Countries

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The Mathworks Product Family
DAQ cards Instruments
Slide Courtesy of The MathWorks
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The Mathworks Design Environment

• Top-Down Design
• Design Test System Behavior Early in the Design
  Process
• Create Validated Reference Design
• Detect Design Flaws Early
• Reduced Design Risk Cost
• Reduced Time-to-Market

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MATLAB Environment
Current Working Directory
Simulink
Variables
Results of Commands Errors, etc.
Command History
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Simulink

• Hierarchical Block Diagram Design Simulation
  Tool
• Digital, Analog/Mixed Signal Event Driven
• Visualize Signals
• Integrated with MATLAB

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Simulink Blockset Libraries

• Simulink
• Sources
• Sinks
• Continuous
• Discrete
• Non-Linear
• Math
• Fixed-Point Blockset
• DSP Blockset
• Communications Blockset
• SimPowerSystems Blockset
• Others

Altera DSP Builder
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Matlab / Simulink Model Created with Altera DSP
Builder Libraries
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Design Flow with DSP Builder
(???)
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What Is DSP Builder?

• Links MATLAB/Simulink Design Environment to
• Quartus II Development Tool for Altera FPGAs
• Automatic HDL Code Generation from Simulink Model
  Generated by DSP Builder Libraries
• Generates Bit Cycle Accurate Models for DSP
  Functions
• Automatic Generation of HDL Testbench
• Integrated Intellectual Property (IP) Library
  Support
• Enables Rapid Prototyping with Altera DSP
  Development Board
• Facilitates Integration of Complex DSP Functions

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DSP Builder Overview
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Altera DSP Builder Libraries

• AltLab
• Arithmetic
• Boards
• Complex Type
• Gate Control
• IO Bus
• Rate Change
• SOPC Builder Links
• State Machine Functions
• Storage
• MegaCore Functions
• Video and Image Processing

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Design Flow Overview

1. Create Design in Simulink Using Altera Libraries
2. Simulate in Simulink
3. Add Signal Compiler to Model
4. Create HDL Code Generate Testbench
5. Perform RTL Simulation
6. Synthesize HDL Code Place Route
7. Program Device
8. Signal Tap II Logic Analyzer

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Step 1- Create Design in Simulink Using Altera
Libraries

• Drag Drop Library Blocks into Simulink Design
  Parameterize Each Block

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Parameterization of IP Megacores
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Step 2 - Simulate in Simulink
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Step 3 - Add Signal Compiler to Model to
Generate HDL code
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Step 4 - Create HDL Code Generate Testbench
altrfir32.mdl
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HDL Code Generation
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DSP Builder Report File

• Lists All Converted Blocks
• Port Widths
• Sampling Frequencies
• Warnings Messages

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Step 5 Perform RTL Simulation
( ModelSim )

1. Set working directory (File gt Change Directory)
2. Run TCL file (Tools gt Execute Macro)

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Perform Verification
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Step 6 - Synthesize HDL Place Route
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Step 7 Program Device
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Step 8 - SignalTap II Logic Analyzer

• Embedded Logic Analyzer
• Downloads into Device with Design
• Captures State of Internal Nodes
• Uses JTAG for Communication

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SignalTap II Logic Analyzer
Imported Data
Imported Plot
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Design Flow Review with DSP Builder

1. Create Design in Simulink Using Altera Libraries
2. Simulate in Simulink
3. Add Signal Compiler to Model
4. Create HDL Code Generate Testbench
5. Perform RTL Simulation
6. Synthesize HDL Code Place Route
7. Program Device
8. Signal Tap II Logic Analyzer

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Quartus II Assignments Settings
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Stratix II DSP Development Board
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Stratix II DSP Board Block Diagram
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(No Transcript)
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Demos Provided with DSP Builder
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??? Altera DSP Builder???

• AltLab?
• ???
• ?????
• ??????
• Rate Change???
• ??????
• ???(Storage)???
• MegaCore????
• ??

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Altera DSP Builder Libraries

• AltLab
• Arithmetic
• Boards
• Complex Type
• Gate Control
• IO Bus
• Rate Change
• SOPC Builder Links
• State Machine Functions
• Storage
• MegaCore Functions
• Video and Image Processing

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1?AltLab?(1)

• AltLab?????????????,???????????RTL??VHDL???

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AltLab Library

• Signal Compiler
• HDL SubSystem
• Build Hierarchical System
• HDL Import
• SignalTap II Block
• SignalTap II Analysis
• BP Bus Probe
• Device programmer
• HIL
• Quartus II Global Project Assignment
• Quartus II Pinout Assignment
• VcdSink
• SubSystem Builder
• Creates Black-Box

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1?AltLab?(2)

• SignalCompiler??
• SignalCompiler???DSP Builder?????,
• ??????
• ?Simulink?????????RTL VHDL
• ??VHDL testbenches
• ??Verilog testbenches
• ??Quartus II??Verilog HDL????
• ?Simulink?????VHDL testbench???txt???????
• ??Tcl ????Quartus II???
• ?????LeonardoSpectrum?Precision RTL
  Synthesis?Synplify?ModelSim?????Tcl??
• ??Quartus II???????
• ??PTF????,??????SOPC Builder
• ????SignalTap II (.stp) ??
• ??Quartus II??????(.bsf) ?

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1?AltLab?(3)

• SignalCompiler??
• ???Simulink???????Simulink????,?????????VHDL???,??
  ?SignalCompiler??????sc_altera??????????

Update DiagramSignalCompiler?????Simulink????????
???DSP Builder?????? AnalyzeSignalCompiler??????
?????mdl??,?????????????DSP Builder???????????????
???????????? Skip Analyze???????
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1?AltLab?(4)

• ????????????????????????????????????????????????
  ???????????reset?????????SignalTap
  II???????????????????SOPC ptf???????Verilog???
• ?????????????Signal Compiler???????,
  ???????,?MDL???VHDL,?????Tcl????
  ?????VHDL????????Quartus II???????????DSP???????
  ???????DSP?????
• ???Project Info??????????Report
  File???SignalCompiler?????????

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AltLab HDL SubSystem

• Create Hierarchical Design
• Separate HDL Code for Each Subsystem

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AltLab HDL SubSystem (cont.)
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2????

• ?????????????????,??????????????Use Dedicated
  Circuitry????,?????????Altera tratix II?Stratix?
  Stratix GX?Cyclone II????DSP??????

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Arithmetic Library

• Comparator
• Divide
• Gain
• Increment Decrement
• Magnitude
• Multiply Accumulate
• Multiply Add
• Parallel Adder Subtractor
• Product
• Sum of Partial Products
• Integrator
• Differentiator

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Arithmetic Library Multiply Add
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Arithmetic LibraryDifferentiator Integrator
BlocksEx CIC Filter(????????? )
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Arithmetic LibraryAdder Gain BlocksEx IIR
Filter(????????? )
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3?I/O????????

• ?????????????????????bit ?????????????

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Bus Manipulation AltBus
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AltBus Modes

• Input Output Port
• Defines Hardware Boundaries
• Converts Floating-Point to Fixed-Point
• Internal Node
• Defines Internal Hardware Node Widths
• Converts SBF Formats
• Constant
• Implements Constants in Hardware
• Black Box
• Defined Later

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Bus Manipulation Bus Conversion
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IO Bus Library (cont.)Ex Floating Point
Operation
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Ex Floating Point Operationwith IO Bus
Library Blocks (Cont.)
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BP Bus Probe
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4???????
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Complex Signals Library

• Butterfly
• Complex Multiplexer
• Complex Conjugate
• Complex Delay
• Complex Product
• Complex AddSub
• Complex Constant
• Complex to Real-imag
• Real-imag to Complex

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ButterFly

• Implement Decimation in Time FFT Butterfly
• a,b,W,A,B Are Complex Number (Signed Integer)
• axjX byjY W vjV
• A abW B a-bW
• A (xyv)YV j(XYv-yV)
• B (x-yv)-YV j(X-YvyV)

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Complex Real-Imag to Complex

• X a Bj
• Conjugate
• Conjugate(X) a - Bj
• Invert
• Invert(X) -a - Bj

• X a Bj
• Y C Dj
• Multiply
• X Y (AC BD) (AD BC)j

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Gate Control Library

• Case Statement
• If Statement
• Logical Bit Operator
• Logical Bus Operator
• Single Pulse
• LUT
• N-to-1 Multiplexer
• 1-to-N Demux
• Decoder
• Bitwise Logical Bus Operator

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Gate Control LibraryEx Convolutional
Interleaver
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5????(Storage)???
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Storage Library

• Delay
• Down Sampling
• Dual-port RAM
• FIFO
• LFSR Sequence
• LUT
• Parallel to Serial
• Pattern
• ROM EAB
• Serial to Parallel
• Shift Taps
• Up Sampling

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Storage Shift Taps
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ROM EAB Shift Taps BlocksEx Polyphase Filter
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Memory Delay BlockEx 2D Filter
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6?Rate Change???(1)

• ????????DSP Builder???Delay?Increment
  Decrement?????????Simulink?VHDL????????????Simulin
  k?Solver,??????
• ??Fixed-step
• ??discrete
• (no continuous state)
• ??Single Tasking??

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6?Rate Change???(2)

• ClockAltr?? ????????????????
• PLL?? ????????????????????
• Multi-Rate DFF?? ?????????
• Tsamp ?? ??????????????

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6?Rate Change???(3)
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Rate Change Multi-Rate DFF

• Synchronize data path intersections
• involving multiple rates

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Rate Change Tsamp PLL BlocksEx Polyphase
Filter
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7?SOPC Builder Link(1)

• Nios II???????????????????????????,??????????????
  ????Nios II????????RISC CPU????????Cygnus?Red
  Hat??GNUPro???
• ??????SOPC???????????????????,??SOPC
  Builder????SOPC Builder???????????????
• ??Avalon?????
• ??Nios II????????????????????

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7?SOPC Builder Link(2)

• ?????????VHDL?,SignalCompiler????class.ptf???Quart
  us II???????????SOPC Builder? ???DSP Builder
  SOPC Builder?????

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SOPC Builder Library DSP Acceleration

• Custom Peripheral
• Interface to Nios Through Avalon Bus
• Custom Instruction
• Adds Customized Logic to Nios ALU

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What is SOPC Builder?
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SOPC Builder LibraryCustom Instruction

1. Add Custom Instruction Blocks to Simulink Model

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SOPC Builder Library Custom Peripheral

1. Add Avalon Ports to Simulink Model

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SOPC Builder Library Avalon Blocks
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SOPC Builder Library Avalon Blocks
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8?DSP????
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Board Library
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9??????
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10?MegaCore ????

• Altera ?MegaCore???Altera?PLD???????????????,???M
  egaCore???????Altera?MegaWizard Plug-In
  Manager???????
• OpenCore Plus??????????????????????,??????????????
  ???,?????MegaCore???????
• DSP Builder??????IP?
• FIR Compiler
• IIR Compiler
• Reed-Solomon Compiler
• Viterbi Compiler
• FFT Compiler
• NCO Compiler

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Alteras IP Megafunctions

• Shrink-Wrapped Functions Customers can Drop into
  Altera FPGA Designs
• Optimized for Altera Architectures
• Easily Parameterized through MegaWizard Plug-in
  Manager

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Megacore IP in DSP Builder
DSP IP Type
FIR Compiler Filtering
FFT/IFFT Compiler Transforms
NCO Compiler Signal Generation
Reed-Solomon Compiler Error Detection/ Correction
Viterbi Compiler Error Detection / Correction
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FIR Compiler
1.Generate Floating-Point Coefficients based on
Filter Parameters 2. Scale Coefficients to
Fixed-Point Values 3. Select Input/Output
Specifications 4. Determine Filter
Architecture 5. Select Output Simulation Files
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Numerically Controlled Oscillators (NCO)

• Purpose
• To Generate a Discrete-Time, Discrete-Value
  Waveform Approximating a Continuous Waveform to a
  Defined Precision
• Primary Application Area
• Direct Digital Synthesis (DDS) of Sinusoidal
  Waveforms
• - I-Q Modulation
• - Carrier Recovery
• - Pilot Generation.

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Advanced Features

• Black Boxing
• Modelling Guidelines
• - Clock Design Rules
• - Multi-Rate Designs
• - Data Width Propagation
• - Automatic Sign Extension
• - Word Growth

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Black-Boxing

• What is a black-box and why is it used?
• Module or Group of Blocks Left Unprocessed by DSP
  Builder
• Surrounding Blocks Still Converted to HDL
• Allows HDL Code to Be Added to Simulink Design
• Use Blocks, C-Based Model or M-File for Simulink
  Simulation
• Output Netlist Includes Port Connections to
  Black-Box
• Black-Box Code is Inserted by Quartus II
• Uses Altbus Blocks in Block Box Input Output Mode

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Replace With Black Box
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Looking Under Black Box
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AltBus Black Box Mode

• Black Box Input Output Port
• Creates Black Box
• Not Converted to HDL
• Port Connections Remain

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???(?)

• ?????????????????

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???(?)

• ??????DTMF????

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????

• ? ? !