Fault-Tolerant Clustering for FPGAs

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Fault-Tolerant Clustering for FPGAs

• Jason Cong and Brian Tagiku
• VLSI CAD Laboratory
• Computer Science Department
• University of California, Los Angeles
• cong,btagiku_at_cs.ucla.edu
• http//cadlab.cs.ucla.edu/

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Outline

• Background
• Problem Model and Formulation
• Fault-Tolerant Clustering
• Fault Assignment and Reconfiguration
• Future Work

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Previous Work

• Flat (Non-Hierarchical) FPGAs
• Hatori et al. (Toshiba, 1993) Spare rows of
  CLBs
• Howard et al. (Univ. of York, 1994) Spare
  blocks of CLBs
• Hanchek and Dutt (Intel/UIUC, 1996) Node
  Covering, each CLB assigned a node to cover
• Lach et al. (UCLA, 98) Tiling, FPGA partitioned
  into tiles and alternate configurations for each
  tile precomputed
• Hierarchical FPGAs
• Lakamraju and Tessier (Univ. of Mass., 2000)
  Spare elements in each block level

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Related Work

• Fault covering in memory arrays
• Spare row and columns available
• Must use spares to cover entire row or column in
  which faults occur
• Difficulty lies in finding a set of covering rows
  and columns
• Comparison to fault tolerance in FPGAs
• A set of spares to cover faults is easy to find
• Difficulty is finding a set that allows a target
  delay to be met

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Hierarchical FPGAs

• 2 level, hierarchical circuit logic
• Level 0 Blocks LUTs
• Level 1 Blocks Clusters of LUTs
• Uses locality of interconnections to improve
  circuit performance

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Redundancy in FPGAs

• LUTs can fail with some probability
• Allocate extra components (e.g. LUTs) into the
  system
• Re-route inputs and outputs to a spare LUT
• Ideally, want the spare LUT to be close to the
  failure so that delay does not increase

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Redundancy in FPGAs

• LUTs can fail with some probability
• Allocate extra components (e.g. LUTs) into the
  system
• Re-route inputs and outputs to a spare LUT
• Ideally, want the spare LUT to be close to the
  failure so that delay does not increase

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Redundancy in FPGAs

• LUTs can fail with some probability
• Allocate extra components (e.g. LUTs)
• Re-route inputs and outputs to a spare LUT
• Ideally, want the spare LUT to be close to the
  failure so that delay does not increase

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Redundancy in FPGAs

• LUTs can fail with some probability
• Allocate extra components (e.g. LUTs) into the
  system
• Recover from defects by using spare LUTs
• Ideally, want the spare LUT to be close to the
  failure so that delay does not increase

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Redundancy in FPGAs

• LUTs can fail with some probability
• Allocate extra components (e.g. LUTs) into the
  system
• Re-route inputs and outputs to a spare LUT
• Ideally, want the spare LUT to be close to the
  failure so that delay does not increase

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Fault Tolerant Clustering

• Inputs
• A DAG G (LUT Netlist)
• An HFPGA with k clusters of c LUTs
• Inter/Intracluster edge delays
• Probability of LUT defects
• Target delay D
• Goal
• Map G into the HFPGA to maximize probability of
  achieving delay D after reconfiguration of
  failures

A
B
C
D
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Motivational Example
Probability of LUT failure 0.1
Maximum intercluster edges along path Probability
1 0.89
2 0.09
failure 0.02
Maximum intercluster edges along path Probability
1 0.97
2 0.01
failure 0.02
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Dynamic Programming Heuristic

• Use a dynamic programming matrix A
• Each entry Ai,j,k stores a clustering solution
  of node i and its predecessors such that
• Exactly j clusters are used
• Arrival time at i is at most k
• The probability of achieving delay k is maximized
• Allows node duplication
• Assumes constant fan-in

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DP Heuristic Performance

• 10 failure rate
• Intracluster edge delay 0
• Intercluster edge delay 3
• LUT delay 1
• 8 clusters each of 3 LUTs
• Target delay of 7

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DP Heuristic Performance
Min-delay clustering Achieves delay 7 with
probability 0.28
DP clustering Achieves delay 7 with probability
0.39
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Difficulties

• Best known algorithm for calculating probability
  distribution of delays is exponential
• Doesnt specify how to reconfigure a circuit

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Failure Assignment

• Inputs
• A DAG G
• An HFPGA with k clusters of c LUTs
• Inter/Intracluster edge delays
• Target delay D
• A mapping of G into the FPGA
• A set of failed LUTs
• Goal
• Reassign failed LUTs to spare LUTs so that the
  delay D is still met.

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More Difficulties

• Failure Assignment is NP-Complete
• Even with fixed cluster sizes c 4
• Even if spares are guaranteed to be non-defective
• Even if we are guaranteed at least m spares per
  cluster
• Even if no more than P percent of the LUTs fail
• These results seem to imply that Fault Tolerant
  Clustering is also a hard problem

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Online Failure Assignment

• Defects and faults announced online (one at a
  time)
• We must assign a fault to a spare when announced
• We cannot change our mind at a later time
• Related Problems
• Online Routing
• Faults need to be connected to spares
• ?(log n)-competitive algorithm known
• Online Bipartite Matching
• Faults need to be matched to spares
• O(log3 n) randomized algorithm for metric cases
  known

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Future Work

• Try to modify inputs to Failure Assignment
• So problem admits a poly-time exact (or
  approximation) algorithm
• Restrict the given mapping to allocate spares in
  some manner
• Use results from Failure Assignment to guide
  clustering algorithms
• Generalize delay model so that LUT placement is
  also considered

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Future Applications

• Nanoscale FPGAs
• Integrate with BIST to make a self-repairing
  system
• Produce profitable yield despite high defect rates