Paul Scherrer Institute

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Paul Scherrer Institute
Stefan Ritt
The role of analog bandwidth and signal-to-noise
in timing for waveform digitizing
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Timing measurement

• How can we measure timing in an optimal system?

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The ideal digitized signal

• No noise
• Always same height
• Derive time from thresholdcrossing with
  interpolation

Threshold
Timing determined by aperture jitter
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Aperture jitter
Flash ADC
Switched CapacitorArray
Datasheet AD9222 (Analog Devices)
PLL

• Determined by write switch jitterplus inverter
  jitter
• Measurements indicate typicalvalue 2-5 ps for
  current designs

• Data sheet lt1ps
• Measured indirectly thoughside-band of sine
  signal
• AD Application Note AN50150fs (clk) 190fs
  (ADC)

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Aperture jitter of clock distribution
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The varying digitized signal

• Signals with different amplitudetrigger at
  different times(time walk)

Upper threshold
Lower threshold

• Time walk correction
• Multi-level threshold
• Constant-fraction discrimination

J.-F. Genat et al., arXiv0810.5590 (2008)
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Effects of analog BW

• How does the analog bandwidth affect the timing ?

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Realistic signal with noise
Effect of rise time
Noise affects timing!
voltage noise band of signal
timing jitter arising from voltage noise
Noise
Timing
timing jitter is much smaller for
faster rise-time
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Nyquist-Shannon Theorem

• If a function x(t) contains no frequencies higher
  than F Hertz, it is completely determined by
  giving its ordinates at a series of points spaced
  1/2F seconds apart.

Nyquist-Shannon fulfilled
Nyquist-Shannon not fulfilled

• If a detector produces frequencies up to 500 MHz
  (0.6 ns rise time), all information from that
  detector is recorded if sampled at 1 GSPS with
  good enough signal-to-noise (SNR) ratio
• Sampling speed above Nyquist adds redundant
  points which improve the SNR

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Does higher sampling speed help?

• Higher sampling speed adds only redundant points
  if Nyquist is fulfilled
• If noise comes from chip ? reduce noise v2
• Equivalent to double sampling of points

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How is timing resolution affected?
voltage noise Du
signal height U
timing uncertainty Dt
rise time tr
Simplified estimation!
number of samples on slope
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How is timing resolution affected?
Assumes zeroaperture jitter
U Du fs f3db Dt
100 mV 1 mV 2 GSPS 300 MHz 10 ps
1 V 1 mV 2 GSPS 300 MHz 1 ps
100 mV 1 mV 20 GSPS 3 GHz 0.7 ps
1V 1 mV 10 GSPS 3 GHz 0.1 ps
today
optimized SNR
next generation
next generation optimized SNR
includes detector noise in the frequency region
of the rise time and aperture jitter
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Effect of S/N

• S/N ratio goes linearly into timing resolution!
• Analog BW and sampling speed will soon hit some
  hard limits (3-5 GHz, 20 GSPS)
• Preamplifier makes sense if detector noise is
  smaller than SCA internal noise
• In the end, higher timing resolution will be the
  battle of noise? Erics talk tomorrow

PCB
SCA
f
ADC
Det.
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What limits the BW?

• Which are the crucial points in the signal chain?

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Signal Chain

• Detector (covered in next talks)
• Connector (LEMO connector has a BW of 500 MHz)
• Cable (RG58 5 m has a -3db BW of 1 GHz)
• PCB
• Preamplifier
• Chip package
• On-chip bus
• Analog cell switch
• Storage capacitor

PCB
Chip
Det.
Cpar
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Amplifier
750 MHz
40pF
Cpar
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Effects from the chip

• ? Tomorrows talk

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Conclusions
Optimize BW of detector
Optimize BW of transmission
Optimize S/N for digitization
Fit digitization B/W to signal
Fulfill Nyquist-Shannon