ESE Section Status

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ESE Section Status

• Personnel
• We are still three people down from April last
  year. I will be hiring soon but there will not
  be resource improvement for several months.
• Ex-support projects
• CDF DAQ and silicon tracker support is very low
  level, but spiky. Still some issues with
  radiation damage and speeding up the readout
• D0 DAQ support is capably handled by ESD along
  with CDF DAQ.
• D0 Trigger distribution system needed a four week
  repair and test cycle for a noticeable quantity
  of boards.
• D0 Mixer system support is very low level, but
  spiky. Diagnostics requests mostly.
• D0 L2 trigger processor (Alpha/Betas) support
  quiet and assumed to be done.
• Beams Recycler BPM Upgrade is working well but
  not commissioned. CD support is capably handled
  by ESD.
• CDF Silicon and DAQ RunIIb upgrades are wrapping
  up assembly and testing of individual wedges.
  Minimal effort from ESE.
• Total effort between 1 and 2 FTE for the previous
  12 months.

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CDF Area
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ESE Project D0 VRB Controller debugging

• Abstract and Goals
• ESE asked to get VRB Controller modules into
  serviceable condition. The ESE evaluation phase
  was restarted after the VRB controllers meet
  their original specification. There are two
  versions of the module.
• Leader(s) Don Lincoln, Ted Zmuda
• Stakeholder Orgs D0, CEPA/ESE
• Participants and Effort Ted Zmuda, Mark Bowden,
  Thinh Pham
• Timeline Schedule Start May 2003, Ongoing,
  Run2a D0
• Deliverables Error free operation of both
  versions of the module.
• Overhaul of VRB Controller modules not likely.
• Plans Current firmware under test and may be
  satisfactory
• Comment There were two VRBC layouts which
  complicated the debugging. One design has been
  patched to match the other. ESE is not planning
  to support this module beyond patching the
  firmware to fix bugs.
• WBS 50.02.04.02

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VRBC Test Stand
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ESE Project D0 Detector Luminosity Monitor
Firmware

• Abstract and Goals
• D0 designed a board to be used in both the
  Trigger Luminosity Input and the DAQ Luminosity
  Monitor. D0 asked ESE to write the firmware for
  the Trigger version.
• Leader(s) Rich Partridge, Brendan Casey,
  Rick Kwarciany
• Stakeholder Orgs D0, CEPA/ESE
• Participants and Effort Rick Kwarciany
• Timeline Schedule Start April 2003,
  Ongoing, Run2a/b D0
• Deliverables Firmware, Support User Requests
• Plans Iterate testing and debugging until the
  requirements are met.
• Comment Rick has completed firmware that
  accomplishes
• the first requirements. Testing is waiting for
  TDC work.
• WBS 50.02.04.02

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Luminosity Test Stand
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ESE Project Tevatron Ionization Monitor.

• Abstract and Goals Produce DAQ buffer card for
  new Ionization Profile Monitor in the Tevatron.
  Design, Prototype, production and support of
  module. Major firmware development effort.
• Leader(s) Adreas Jansson, Hogan Nguyen, Mark
  Bowden, Rick Kwarciany.
• Stakeholder Orgs AD, CEPA/ESE
• Participants and Effort ESE DAQ Team
• Timeline Schedule Prototype buffer testing
  date April.
• Deliverables Operational boards in DAQ system
  2004
• Plans Prototype schematic begun, layout next.
  Firmware being designed.
• Comment Utilizing development done for level 1
  buffer for BTeV DAQ to quickly produce a version
  for AD.
• WBS 50.01.13

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FPGA
12 channel (X 2.5 Gbps) Optical Receiver
DDR Memory (3 GBytes)
IPM/BTeV L1 Buffer Prototype
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ESE Project Tevatron BPM DAQ
Page 9
June 25, 2003

• Abstract and Goals
• Design DAQ for replacement Tevatron Beam
  Position Monitor System.
• Leader(s) Steve Wolbers, Bob Webber, Vince
  Pavlicek
• Stakeholder Orgs Beams, CEPA/ESE, CEPA/APS
• Participants and Effort Vince Pavlicek, Mark
  Bowden
• Timeline Schedule Prototype in summer, install
  in Fall.
• Deliverables DAQ hardware, purchase or design
  and construct.
• Plans See http//wwwserver2.fnal.gov/tevbpm/in
  dex.html.
• Comment
• WBS 50.01.13

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ESE Project D0 L1 Calorimeter Test Waveform
Generator
Page 10
June 25, 2003

• Abstract and Goals
• Design, fabricate commission a Waveform
  Generator module that will assist testing of the
  D0 Level 1 Calorimeter front-end board.
• Leader(s) Hal Evens (Nevis), Stefano
  Rapisarda
• Stakeholder Orgs D0, CEPA/ESE
• Participants and Effort Stefano Rapisarda,
  Gustavo Cancelo
• Timeline Schedule Start Jan 2003. Prototype
  tested, production specifications underway.
  Run2b D0
• Deliverables 4-20 Production modules Summer 2004
• Plans Prototype successfully tested with
  Saclay prototype ADF, Michigan State will
  complete ADF production. Timing enhancements
  SCL interface being added.
• Comment
• WBS 50.02.04.02

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ESE Possible Project SVX DAQ Run IIb upgrade
Page 11
June 25, 2003

• Abstract and Goals SVX DAQ upgrade, including
  FTM board and modifications to other modules as
  needed.
• Leader(s) Peter Maksimovic (Johns Hopkins) ,
  Guilherme Cardoso
• Stakeholder Orgs CDF/SVX, CEPA/ESE
• Participants and Effort Guilherme Cardoso, Jim
  Franzen
• Timeline Schedule Being defined
• Deliverables FTM design and production including
  firmware,
• Support User Requests
• Plans Waiting for CDF collaboration decision.
  
• Comment Includes consultation on the new SRC
  being designed at Johns Hopkins.

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ESE Effort Pixel RD Test Beam Support.
Page 12
June 25, 2003

• Abstract and Goals BTeV test beam support
• Leader(s) Simon Kwan, Marcos Turqueti.
• Stakeholder Orgs BTeV, PPD, CEPA/ESE
• Participants and Effort Marcos Turqueti
  Lorenzo Uplegger
• Timeline Schedule Current, Ongoing, BTeV
• Deliverables Test Beam FPIX1 FPIX2 telescope
  planes.
• Operational support during Test Beams.
• Plans First 6 FPix1 planes delivered and
  working at MTest,
• Additional pre-FPix2 planes in process.
• Waiting for Beam.
• Comment Inserted here because of the primarily
  support nature of this effort

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Possible ESE Project D0 SCL Diagnostic Board.
Page 13
June 25, 2003

• Abstract and Goals Modify the Serial Command
  Link (SCL) receiver firmware such that a test
  stand can be safely connected to the running
  detector SCL system to allow debugging noise
  issues in the detector that are not reproducible
  on isolated test stands.
• Leader(s) Marv Johnson, Ted Zmuda
• Stakeholder Orgs D0, CEPA/ESE
• Participants and Effort Ted Zmuda, Thinh Pham
• Timeline Schedule TBD, awaiting specification
  meeting
• Deliverables Modified firmware
• Plans
• Comment Ron Rechenmacher asked Ted for a
  similar change, which has become popular. Now we
  need to define what exactly D0 wants and needs
  for this diagnostic task. D0 really wants this
  but it needs to get pop up on their stack.

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Possible ESE Project Level 1 Calorimeter
daughter card
Page 14
June 25, 2003

• Abstract and Goals D0 designed the card and
  did the schematic. ESE will provide the PCB
  layout and production but no testing or support.
• Leader(s) Dan Edmonds, Stefano Rapisarda
• Stakeholder Orgs D0, CEPA/ESE
• Participants and Effort Stefano Rapisarda, Jim
  Franzen
• Timeline Schedule Waiting for information and
  decisions.
• Deliverables Layout and modules from PCBs
  Parts.
• Plans
• Comment Proposed in 2002, then repeatedly
  back-burnered

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ESE Effort Lattice Gauge Links
Page 15
June 25, 2003

• Abstract and Goals High Speed Link design,
  prototype and production. Was a project now being
  down graded.
• Leader(s) Don Holmgren, Bill Haynes
• Stakeholder Orgs Lattice Gauge, CCF/FTP,
  CEPA/ESE
• Participants and Effort Bill Haynes, Greg
  Deuerling
• Timeline Schedule Prototype testing FY04
• Deliverables Prototype Links
• Plans Given working prototypes, build
  production units.
• Comment A prototype enabler for the ongoing
  section RD effort in high speed links.
• WBS 50.02.04.03

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Link Prototype
This is a picture of the 8-channel serial-link
card that is capable of a data rates up to 3.5
Gbs per channel
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End