Testing

1

• Testing
• using a VHDL testbench
• methods of testing
• --logic simulation
• --delay models
• logic simulation

2
Using a VHDL testbench (Hamblen, pp. 96-97) UUT
unit under test testbench VHDL wrapper
to test UUT testbench code is not usually
synthesized In our Altera Tools
configuration, we should use a test vector
file (file.vec) instead, since the Compile step,
which generates timing information,
also synthesizes the design
Testbench
Generate Stimulus
UUT
Monitor Response
3
testprocess variable tD,tclk,trst,ten,toutstd_l
ogic file vector_file text is in DFF.txt
variable llinevariable vector_timetime
variable rreal variable space character
begin while not endfile(vector_file) loop
readline (vector_file,l) read (l,r)
vector_time r1 ns if (nowltvector-time)
then wait for vector_time - now end if
read (l.space) read(l,tD,tclk,trst,ten)
read(l,space) read(l,tout) assert tout
out report mismatch DlttDclocklttclkrese
tlttrst enableltten end loop assert
false report test donewait end process end
full
Example testbench--test a DFF (lec. 5) entity
testbench is end testbench library ieee use
ieee.std_logic_1164.all use std.textio.all use
ieee.std_logic_textio.all use work.count_types.al
l architecture full of testbench is component
DFF port (D, clock, reset, enablein std_logic
Q1 out std_logic) end
component signal D,clock,reset,enable,outstd_log
ic begin uut DFF port map (DgtD,
clockgtclock, resetgtreset,
enablegtenable,outgtout)
4
Associated vector_file (excerpt) INPUTS
tD,Tclk,trst,ten PATTERN 0000 1010 OUTPUTS
tout PATTERN X 0 Basically this file
corresponds to the file DFF.txt in the example
above
5
Testing using logic simulation example of
design verification testing uses model of
system (VHDL testbench is an example, as is
Altera simulator) can test both functionality
and some timing delays, race conditions,
oscillations) can generate output values for use
in physical test
6
Delay models basic model transport
delay--multiples of some fixed unit ex for
delays of 15,20,30 ns, scale to 3,4,6 units,
where 1 unit 5 ns may also model separate rise
and fall delays if delay is given by
manufacturer as an interval (e.g., 5-10 ns), can
use an ambiguous delay with an interval during
which value is not known
7
Ex SET/RESET D Flip-flop inputs are
S,R,D,Clk must give output in terms of delay
for all of these signals must also consider
internal state 0 or 1
8
Must also model transient pulses static
hazard--e.g., 0u0 dynamic hazard--occurs
during 0--gt1 or 1--gt 0
9
High-speed circuits must also include wire
delays
10
Logic simulation Functional testing--validate
the correct operation of a system with respect to
its behavioral specifications does not use
structure of the UUT (treats it as a black
box) Q how do we choose a set of test
vectors? We can choose a specific fault model
or we can focus on the desired fault-free
behavior
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Some function representations we can use in
testing example for the function Z given by
x1 x2 x3 Z 0 0 0 1 a. primitive
cubes b. BDD 0 0 1 1 (binary
decision 0 1 0 0 x1 x2 x3 Z diagram) 0
1 1 1 x 1 0 0 Z 1 0 0 1 1 1
x 0 1 0 1 1 x 0 x 1 1 1
0 0 0 1 1 1 1 1 1 0
x1
0
1
x2
x2
(should be reduced if possible)
x3
x3
x3
x3
0
0
0
1
1
1
1
1
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may need unknown state (u or X) extension to
boolean logic AND(0,u) 0 AND(1,u) x
AND(u,u) u OR(0,u) u OR(1,u) 1
OR(u,u) x NOT(u) u (note we do not
assume the opposite of u--this can lead to
errors)
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Many levels are possible register-level (use an
RTL or register transfer language) functional-l
evel model system as interconnected
components gate-level transistor-level (logic,
not circuit-level) mixed-level
14
Testing without a specific fault model a.
Heuristic methods b. Component-based
methods c. Methods based on traversing a BDD
(may be too time-consuming) d.
pseudoexhaustive tests for small circuits
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Example of a pseudoexhaustive test
a b c 0 0 0 0 1 0 1 0 1 1 1 1
A
X
B
Y
C
Since each output depends only on 2 inputs, we
can test all possibilities with 4 vectors instead
of 8 here a,b values test all inputs for X b,c
values test all inputs for Y