Data Acquisition ET 228 Chapter 14.0-3

1
Data Acquisition ET 228Chapter 14.0-3

• Analog and Digital
• Digital to Analog Converters (DACs)
• DAC Resolution
• DAC Offset Errors
• DAC Gain Error
• Digital to Analog Conversion Process
• Voltage Output DACs

2
Data Acquisition ET 228Chapter 14.0-3

• Analog and Digital
• Some Real world processes produce analog signals
• Voices and music
• Pictures
• Letters and Decimal numbers
• Digital systems use binary signals
• ASCII code for a gtgt 1100001
• What are some other types of encoding the are
  either currently used or have been used - respond
  in this Weeks topic under the discussion board
  under Angel
• Relative Strengths of Digital Data
• Simplified Storage, retrieval of information
  stored in digital form
• Analog Systems - Cumbersome Expensive

3
Data Acquisition ET 228Chapter 14.0-3

• Analog and Digital
• Relative Strengths of Digital Data
• Simplified Storage, retrieval of information
  stored in digital form
• Analog Systems - Cumbersome Expensive
• Other strengths of digital data - respond in
  this Weeks topic under the discussion board
  under Angel
• Devices
• Digital to Analog Converters (DACs)
• You should be able to identify some common
  devices and services that use these devices
• Some of these have been used on a daily basis for
  many decades and some are new
• Analog to Digital Converters (ADCs in Chapter 15)
• You should be able to identify some common
  devices and services that use these devices

4
Data Acquisition ET 228Chapter 14.0-3

• Digital to Analog Converters (DACs)
• There Various types of DACs
• There are ones that specify output currents
• These can be either current sources or sinks
• Developing an output voltage signal is dependent
  upon circuits external to the DAC
• Voltage Output Types
• Usually the multiple output voltage ranges are
  selectable
• Unipolar or Bipolar Outputs
• DACs with Unipolar outputs usually have their
  outputs range from common to some positive
  voltage
• Especially in devices that operate on batteries
• The maximum output voltages usually are limited
  by the battery voltages
• e.g., 0 -5 volts

5
Data Acquisition ET 228Chapter 14.0-3

• Digital to Analog Converters (DACs)
• There Various types of DACs
• Unipolar or Bipolar Outputs
• Bipolar output DACS usually have their output
  voltage range symmetrically centered on common
• e.g., -5.12 to 5.12 volts, -10.24 to 10.24
  volts, -2.56 to 2.56 volts
• Sometimes the output range can be shifted to a
  new center voltage
• e.g., -2.12 to 8.12 volts (centered on 3
  volts), 4.88 to 15.12 volts (centered on 10
  volts)
• Relationship between Inputs and Outputs
• The relationship is the Transfer Function
• For a given digital input you can expect a
  specific analog output
• Real devices approach the specified transfer
  function

6
Data Acquisition ET 228Chapter 14.0-3

• DAC Resolution
• The number of Distinct Analog Outputs
• A three Bit DAC has a resolution of 8
• A eight bit DAC has a resolution of 256
• Resolution is usually expressed in one of two
  ways
• Resolution 2n, where n of bits
• The resolution of a 10 bit DAC 210 1024
• Resolution just the of bits of the DAC
• The resolution of a 10 bit DAC could be expressed
  as 10-bits
• Can be Unipolar or Bipolar - See Figure 14-1 page
  402
• The Circuit symbol shown in Figure 14-1(a)
  assumes a Unipolar output
• It only shows one input reference voltage
• The other one is assumed to be common

7
Data Acquisition ET 228Chapter 14.0-3

• DAC Resolution
• The number of Distinct Analog Outputs
• Can be Unipolar or Bipolar - See Figure 14-1 page
  402
• A symbol that assumed a bipolar output would have
  a positive and negative input reference
• The chart shown in Figure 14-1(b) graphically
  shows the relationship between digital inputs and
  analog outputs for a Unipolar output 3-bit DAC
• With a 000 input the output common
• With a binary 4 input (100) the output is equal
  to 1/2 of the input reference voltage
• With a digital full scale input of a binary 7
  (111) the output is equal to 7/8 of the input
  reference voltage
• NOTE the book uses a 3-bit DAC for discussion
  only to convey the concepts with out unnecessary
  detail. Figure 14-1 using a 8-bit DAC would need
  256 different output levels

8
Data Acquisition ET 228Chapter 14.0-3

• DAC Resolution
• The number of Distinct Analog Outputs
• Can be Unipolar or Bipolar - See Figure 14-1 page
  402
• chart shown in Figure 14-1(c) graphically shows
  the relationship between digital inputs and
  analog outputs for a Bipolar output 3-bit DAC
• With a 000 input the output (-) Input
  Reference Voltage
• With a binary 4 input (100) the output is equal
  to common
• With a digital full scale input of a binary 7
  (111) the output is equal to 3/4 of the () input
  reference voltage or 7/8 of the difference
  between the () input reference voltage and (-)
  input reference voltage
• With a binary 6 input (110) the output is equal
  1/2 () input reference voltage or 6/8 of the
  difference between the () input reference
  voltage and (-) input reference voltage

9
Data Acquisition ET 228 Chp 14.0-3

• DAC Resolution
• Inputs
• Digital signal
• Reference voltage
• The missing -Voltage reference
• See Figure 14-1 page 402
• Output Voltages
• Always a fraction of the Full-Scale Range (FSR)
• FSR the Input Voltage Reference - the-
  Input Voltage Reference
• e.g. FSR 5.12V - -5.12V 10.24V
• The smallest change in output is the change
  resulting from the input changing by one binary
  digit - e.g., changing from 000 to 001 or any
  other one digit input change ( 100 to 101 or 110
  to 101)
• ?V0 FSR/2n ( ?V0 is also referenced as
  VLSB , where
• LSB
  Least Significant Bit)

10
Data Acquisition ET 228 Chp 14.0-3

• DAC Resolution
• Output Voltages
• The analog output for a full scale digital input
  (e.g., 111 for a 3-bit DAC)
• Vfs VRef (1-1/ 2n), for Unipolar
  output DACS
• Vfs VFSR (1-1/ 2n) the negative
  reference voltage ,
• for Bipolar output DACS
• Review Example Problem 14-1 to 14-3 page 403
• Typical DACs
• Resolutions 8, 10, 12, 14, 16, 18, 20 bits
• Inputs Usually designed for TTL, ECL or CMOS
  voltage levels - Check Specifications

11
Data Acquisition ET 228 Chp 14.0-3

• DAC Offset Errors
• Key way that OP Amps outputs differ from the
  ideal transfer functions
• Offset Error Characteristics
• Offset errors are constant over the range of
  outputs
• Usually given as a percentage of the FSR
• May be referenced to VLSB ,
• aka the V0 for the LSB input
• Usually measured when the DAC has all zeros on
  the input
• See Figure 14-2 on page 406
• Review Example Problem 14-4 on page 405

12
Data Acquisition ET 228 Chp 14.0-3

• DAC Gain Error
• Another key way that OP Amps outputs differ from
  the ideal transfer functions
• Gain Error Characteristics
• Effects the slope of the transfer function
• Changes with the output value
• Thus is zero when all digital zeros are converted
  
• Usually measured with all 1s on the input
• Gain Error () (V11 -VOS/ VRef 1-1/2n)
  - 1 100
• See Figure 14-3 on page 407
• Review Example 14-5 on page 408
• Alternate solution method
• VLSB 5.12V/256 0.02 V 20 mV
• Vfs VRef (1-1/ 2n) 5.12 - (20mV) 5.10V

13
Data Acquisition ET 228 Chp 14.0-3

• DAC Gain Error
• Review Example 14-5 on page 408
• Alternate solution method
• VLSB 5.12V/256 0.02 V 20 mV
• Vfs VRef (1-1/ 2n) 5.12 - (20mV) 5.10V
• 0.2 of FSR 0.2 of VRef for Unipolar output
  DACs 0.002 5.12V 0.01024V
• 5.10 V - 0.01024V 5.0898V
• After class if you need clarification use the
  Canvas discussion board to get suggestions from
  your classmates or e-mail me

14
Data Acquisition ET 228Chapter 14.0-3

• Digital to Analog Conversion Process
• Key Aspects
• DAC Block Diagram
• R-2R Ladder Network
• Ladder Currents
• Ladder Equation
• DAC Block Diagram
• See Figure 14-5 on page 409
• Key Aspects
• Reference voltage
• Connected to resistance network
• VRef
• Digital Inputs
• Number of application methods, e.g., switches,
  FlipFlops, micro controlers, etc.
• Shown using digitally controlled switches

15
Data Acquisition ET 228 Chapter 14.0-3

• Digital to Analog Conversion Process
• DAC Block Diagram
• See Figure 14-5 on page 409
• Key Aspects
• Resistive network
• Performs the actual conversion
• R-2R is a typical DAC resistance network
• Current to Voltage Converter
• Not required on DACs designed for current outputs
• R-2R Ladder Network
• Resistance seen by the reference voltage of
  Figure 14-6 on page 410
• Resistors with the value of R are on the rails of
  the Ladder network the 2R resistors are the rungs
  of the ladder network. 2R resistors have twice
  the resistance of the R resistors

16
Data Acquisition ET 228 Chapter 14.0-3

• Digital to Analog Conversion Process
• R-2R Ladder Network
• Resistance seen by the reference voltage of
  Figure 14-6 on page 410
• Start the analysis at Terminating side with node
  0
• The resistance at node 0 with respect to common
  is referenced as R0
• R0 2R 2R R
• At Node 1
• R1 2R (R R0) 2R 2R R
• At Node 2
• R2 2R (R R1) 2R 2R R
• At Node 3
• R3 2R (R R2) 2R 2R R RRef
• For R-2R Ladder networks RRef always equals the
  rail resistance - R

17
Data Acquisition ET 228 Chapter 14.0-3

• Digital to Analog Conversion Process
• R-2R Ladder Currents
• IRef VRef /R
• I0 1/2n VRef /R
• Review Current Splitting (IRef to I0 )
• See Equations 14-6 on page 410.
• At node 3, IRef has two equal resistance paths
  to ground the rung resistance of 2R and the
  equivalent resistance of 2R through the Rail
  resistor. I3 IRef /2 Half the current flows
  through the rail resistor and ½ thru the rung
  resistor.
• At node 2, . , I2 I3 /2 Half the current
  flows through the rail resistor and ½ thru the
  rung resistor.
• At node 1, ., I1 I2 /2 Half the current
  flows through the rail resistor and ½ thru the
  rung resistor.

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Data Acquisition ET 228 Chapter 14.0-3

• Digital to Analog Conversion Process
• Review Current Splitting (IRef to I0 )
• At node 0, I1 has two equal resistance paths to
  ground the rung resistance of 2R and the
  resistance of 2R from the Rail to ground. I0
  I2 /2 Half the current flows through the rail
  resistor and ½ thru the rung resistor.
• R-2R Ladder Equation
• IOut I0 D
• IOut is the sum of all the rung currents
• I0 is the output current with a 0001 digital
  input
• D the digital input expressed in a Base 10
  number
• Review Example Problem 14-6 on page 411
• Steps
• Find current resolution of the ladder another
  way of asking for I0

19
Data Acquisition ET 228 Chapter 14.0-3

• Digital to Analog Conversion Process
• Review Example Problem 14-6 on page 411
• Steps
• Use the Transfer equation, aka Output-Input
  Equation
• IOut I0 D
• Multiple I0 by the value of D
• Voltage Output DACs
• Figure 14-7 on Page 413
• Major differences with Figure 14-6
• The addition of an inverting Op-Amp Circuit on
  the output
• As configured the curcuit has a voltage gain of
  -1
• This will be apparent in the transfer equation
• The apparent resistance from the (-) Op-Amp input
  for the output of the R-2R ladder R

20
Data Acquisition ET 228 Chapter 14.0-3

• Voltage Output DACs
• Steps leading from the Equation for IOut to VOut
  
• IOut I0 D
• Substitute (1/2n VRef /R) for I0
• IOut (1/2n VRef /R) D
• Account for the inverting Op-Amp circuit
• VOut -(1/2n VRef /R) D Rf
• To simplify the equation lets replace (1/2n
  VRef /R) by its equalivent IO
• VOut - I0 D Rf
• To further simplify -I0 Rf V0
• VOut V0 D