Easy I A Simple Accumulator Processor Instruction Set Architecture ISA

1
Easy IA Simple Accumulator Processor
Instruction Set Architecture (ISA)
Instruction Format (16 bits)
I Indirect bit
2
Easy IA Simple Accumulator Processor
Instruction Set Architecture (ISA)
Instruction Set
Easy all right but universal it is!
3
Easy IMemory Model
8 bits
8 bits
4
Easy IA Simple 16-bit Accumulator Processor
Instruction Set Architecture (ISA)
Some Immediate Observations on the Easy I ISA

• Accumulator (AC) is implicit operand to many
  instructions. No need to use instruction bits to
  specify one of the operands. More bits left for
  address and opcodes.
• Although simple, Easy I is universal. (given
  enough memory). Can you see this?
• Immediate bit specifies level of indirection for
  the location of the operand. I 0 operand in X
  field (immediate). I1 operand in memory location
  X (indirect).

5
Programming the Easy I

• Compute the sum of the even numbers between 1 and
  10

High Level Language Version
int suma 0 int count 0 for (count2 count
lt 10 count 2) suma count
6
Compute the sum of even numbers from 2 to N
Easy I Assembly Language Machine Code Versions
XXXXXXXXXX Dont Care
7
Easy IData Paths (with control points)
A BUS
sel
A D D R E S S B U S
is
Sign-Ext Logic
PC
SXT
D A T A B U S
sel
sel
0
1
le
DI
le
A0
le
A
B
op
ALU
AC
le
IR
Instruction Register
le
8
Sign Extended Logic Module
A BUS
00 01 10
sel
DIlt90gtSign Extended
DIlt90gt
DIlt150gt
DI
9
Easy IMemory Interface
MEMORY
CPU
address
data word
memory op R,W,NOP
10
Easy IControl Unit(Level 0 Flowcharts)
Fetch
Read next instruction
Decode FetchOp
Determine what it does and prepare to do it.
Fetch operands.
Execute
Do it!
We will ignore indirect bit (assuming I 0) for
now
11
Easy IControl Unit(Level 1 Flowcharts)
Reset
Fetch
Fetch Op
Aopr
Sopr
Load
Store
Jump
BrN
What?
Level 1 Each box may take several CPU cycles to
execute
12
Easy IControl Unit(Level 2 Flowcharts)
RESET
reset1
Easy I Byte Addressable Can you tell why?
reset2
Invariant At the beginning of the fetch cycle AO
holds address of instruction to be fetched and
PC points to following instruction
fetch
Each box may take only one CPU cycle to execute
13
Easy IControl Unit(Level 3 Flowcharts)
FETCH
fetch
Memory Bus Operation
Invariant At the beginning of the fetch cycle AO
holds address of instruction to be fetched and
PC points to following instruction
(I0)
(I1)
fetchop
00 11x
opcode
00 00x
00 100
00 101
00 010
00 011
Opcode must be an input to CUs sequential circuit
14
Easy IControl Unit(Level 3 Flowcharts)
FetchOp
X field is an address. Dont extend sign.
fetchop1
Memory Bus Operation
fetchop2
00 11x
opcode
00 00x
00 100
00 101
00 010
00 011
Opcode must be an input to CUs sequential circuit
15
Easy IControl Unit(Level 2 Flowcharts)
AOpr
aopr
Restore fetch invariant
fetch
16
Easy IControl Unit(Level 2 Flowcharts)
SOpr
sopr
fetch
17
Easy IControl Unit(Level 2 Flowcharts)
Load
load1
Must add path from DI to A0
load2
load3
fetch
18
Easy IControl Unit(Level 2 Flowcharts)
Store
store1
store2
fetch
19
Inside the Easy-I PC
ABUS
PC
pcis
0
1
0
2 Adder
PC capable of loading and incrementing simultaneo
usly
00
01
10
11
pcsel
PC
20
Easy IControl Unit(Level 2 Flowcharts)
JUMP
jump
fetch
21
Easy I - Control Unit
Control Unit Combinational Logic
EDBsel
AC15
AOle
AOsel
OpCode
ACle
DIle
I bit
PCis
PCsel
MEMop
Current State
ALUop
Next State
DataPaths state
17
11
clock
22
Easy IControl Unit State Transition Table
23
Easy IControl Unit State Transition Table
24
Easy-I Control Unit Some missing details
4-bit Encodings for States
ALU Operation Table
We know how to implement this ALU !
Control Bus Operation Table
25
Building the Easy-I C-UnitHardwired Approach
Control Unit
ROM
control point signals
next state
11
Memory Unit
2
control bus
11
state
address bus
data bus
4
Data Paths
AClt15gt
5
DIlt1014gt
DIlt15gt