RapidIO Protocol and Model Overview

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RapidIO Protocol and Model Overview
David Bueno 1-14-04 HCS Research Laboratory
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RapidIO Overview

• Targeted for use in embedded systems where
  multiple devices must work in a tightly coupled
  architecture
• Open standard, controlled by RapidIO Trade
  Association (www.rapidio.org)
• Point-to-point, packet-switched interconnect
• Many implementations possible with peak
  bandwidths ranging from 2Gb/s to 64Gb/s
• Networks of any topology possible (generally
  using switches)

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RapidIO Layered Architecture
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RIO Layers Logical and Transport

• Logical Layer- contains protocols necessary for
  end points to process a transaction
• I/O Logical Layer
• Memory mapped remote reads/writes
• No direct support for cache coherence
• Message Passing Logical Layer
• Uses sends and receives with explicit processor
  ID supplied as sender/receiver ID
• Data messages- normal sends/receives
• Doorbell messages- very short, low overhead
  special message (no payload)
• Globally Shared Memory Logical Layer
• Hardware-based cache coherence
• Memory-based mechanism for directory-based
  coherence
• RIO is targeted towards the other two logical
  layers
• All three logical layers may co-exist on the same
  network
• Common Transport Layer
• All logical layers use the common transport layer
• Simple spec provides information to route a
  packet from source to destination

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RIO Layers Physical

• Used for link-level communication
• Two physical layer formats supported
• 8/16 LP-LVDS
• 8-bit or 16-bit parallel interfaces with
  low-voltage differential signaling
• Separate clock and frame pins (and their
  complements)
• LP-Serial 1x-4x
• 1x provides 1 data lane, 4x provides 4 data lanes
• Embeds clock with data
• Both variants use differential signaling
• Both physical formats may co-exist on the same
  network
• Switch can serve as a bride to different physical
  layers
• Many services provided by both physical layers
• flow control, error management, and signal
  acknowledgement (all between linked devices)

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Physical Layer Supported Bandwidths
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Overview of Model Capabilities Logical and
Transport Layers

• RIO Logical Message Passing Layer
• All supported payload sizes
• Support for RIO features such as messages,
  mailboxes, and letters
• End-to-end responses to all messages
• RIO Common Transport Layer
• Both 8 and 16-bit devices IDs supported
• Generally a simple specification
• Current switch model uses a routing table file to
  route packets

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Overview of Model CapabilitiesPhysical Layer

• RIO Parallel Physical Layer
• All valid RIO DDR clock rates supported, as well
  as arbitrary rates
• 8-bit or 16-bit link widths selectable
• All four packet priorities supported
• Packets of higher priority may pass packets of
  lower priority in the fabric
• Packet acceptance or rejection based on number of
  packets currently in buffer and priority of
  incoming packet
• Adjustable thresholds
• Sliding window protocol for link-level
  receiver-initiated flow control
• If receiver doesnt have room, sends a rejection
  and the sender retries

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Overview of Model CapabilitiesSwitches (Routers)

• Eight-port RIO switch
• Number of ports easily changed
• Crossbar architecture
• Buffers at both input and output
• All RapidIO layers present on each switch port

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Ongoing Work

• David
• Testing version 2 of the RapidIO logical,
  transport, and physical layer models
• Increased simulation speed and more realistic
  buffer/priority management
• Adam/Chris
• Learning about MLD, RIO, and the RIO models
• Ian
• Learning and researching GMTI/SAR algorithms and
  planning modeling of these algorithms

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Possible Capabilities to Add

• Error insertion and correction
• Maybe highly relevant for space systems
• Would add significant complexity, as RIO has many
  features related to error detection, correction,
  and recovery
• Transmitter-controlled flow control
• Should provide higher performance, and is an
  optional part of the RIO physical spec
• Additional logical layers (I/O Logical Layer,
  Globally Shared Memory Logical Layer)
• As appropriate for the SAR/GMTI algorithms
• More advanced switch architectures
• Very many tradeoffs to be considered
• Serial physical layer
• If desired, not feasible this semester