Logic Synthesis 4 Compile Strategies

1
Logic Synthesis 4Compile Strategies

• Ahmed Hemani
• Sources
• Synopsys Documentation

2
(No Transcript)
3
The group and the ungroup Commands
design_analyzergt ungroup "U1"
4
Eliminate Unnecessary Hierarchy
5
Remove Glue Logic Between Cells
6
Partitioning Guidelines

• Group related combinational logic and its
  destination register working together
• Eliminate Glue Logic
• Keep related logic in the same block

Good partitioning
7
Partitioning Guidelines -contd

• Partition By Compile Technique
• Structured Logic
• Random Logic

8
Balance Block Size with Run Times
9
(No Transcript)
10
Multiple Instances
Multiple Instances must be resolved! 1.
uniquify 2. compile dont_touch
11
Resolving Multiple Instances - uniquify
uniquify makes a copy of each multi-instantiated
design - each instance gets a unique design
name - DC optimises each copy according to its
specific environment
12
Resolving Multiple Instances compile
dont_touch
If set_dont_touch can be assigned to design
objects this prevents modification of that
design object Caution If placed on un-mapped
design, the design will remain un-mapped
13
Compile First Phase
First phase of compile maps all blocks to gates
without regarding constraints This is done block
by block
Hierarchy is preserved during compile
14
Compile - Second Phase
Second phase of Compile optimises logic to meet
Timing and Area constraints Fixes violations
across hierarchical boundaries i.e. resolves any
driving, loading, timing violations I/O ports
are buffered to match drive strength with load
capabilities
15
Synthesis Strategies Top-Down
16
Top Down Compile StrategyFixing Violations

• If violations are few and small
• Top-level compile -incremental is an option for
  small and medium, sized design.
• The incremental switch makes the compile command
  to optimise only at Gate Level
• If violations are many and large
• Do a Bottom-Up compile approach
• Might benefit from a creation of a design budget
  for each sub-block
• This approach can be done with a high-effort
  compile since the individual blocks are smaller

17
Top Down Compile StrategySimple Compile Mode

• For designs without aggressive timing constraints
• Spends little effort in optimising timing
• Reduces compile time
• Might be used if the tool spends too much time
  during the High Level Optimization
• What does it do?
• Sets hlo_resource_allocation area_only
• hlo_resource_implementation area_only
• Propagates clocks and delays from the top-level
  ports
• Applies default constraints to all blocks
• Compiles the design with these constraints in a
  Bottom-Up fashion
• Performs a top-level clean-up with these
  constraints

18
Top Down Compile Strategy - Example
19
Top-Down Compile

• Read the hieararchy
• Resolve multiple instance
• Constraint the top level design
• Compile
• Problems
• Long Run Times
• Interface Logic Modules

20
Bottom-up Compile

• Create default and block specific constraints
• Compile the sub-designs independently
• Read in the complete hierarchy link
• Apply top level constraints and check if
  constraints are met.
• Characterise sub design with worst violations.
• Write script to save the constraints of the
  sub-design.
• Remove all the designs from the memory
• Read in the RTL of characterised sub-design
• Compile using the saved characterised
  constraints.
• Read in all other compiled sub-designs and the
  top level and link
• Repeat steps 5-10 for other sub-designs

21
(No Transcript)
22
Mixed Compile Strategies

• Use top down for small hierarchies
• And bottom up for the rest

23
Characterizing sub-designs
When you compile subdesigns separately, boundary
conditions such as the input drive strengths,
input signal delays (arrival times), and output
loads can be derived from the parent design and
set on each subdesign. You can do this manually
or automatically.
Manually set_drive, set_driving_cell, set_input_d
elay, set_output_delay, set_load
Automatically characterize
24
Characterize command

• Derive Boundary Conditions
• Timing conditions
• Constraints
• Connection Relations
• Characterize
• cell_list -no_timing -constraints
• -connections -power -verbose

25
Characterize Example
26
Load Calculation
27
Input Delay Calculation
28
Combinatorial Design
29
Sequential Design
30
Characterizing Port Connections
31
Problems with Characterize Compile

• Timing context dealt with one sub-design at a
  time
• Serial nature of flow
• Quality of Result
• Long Run Time
• Budgetting
• Allocate constraints
• Compile designs in parallel

32
(No Transcript)
33
Characterize vs Budget
34
RTL Budgeting Flow
35
Mixed-mode Budgeting Flow
36
Gate-level Budgeting Flow
37
Conclusion

• Know your design
• Functionality
• Constraints
• Technology
• Optimisation
• Think Synthesis early when designing
• Know your tool well
• Employ automation
• Resort to manual only when automation fails
• Use report commands to document and archive the
  synthesis results and constraints.

38
H A P P Y S Y N T H E S I S