The 8051 Microcontroller

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The 8051 Microcontroller

• Chapter 4
• TIMER OPERATION

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• Timer is a series of divide-by-2 flip-flops that
  receive an input signal as a clocking source. The
  clock is applied to the first flip-flop, which
  divides the clock frequency by 2. The output of
  the first flip-flop clocks the second flip-flop,
  which also divides by 2, and so on.
• Timer with n stages divides the input clock
  frequency by 2. The output of the last stage
  clocks a timer overflow flip-flop, or flag, which
  is tested by software or generates an interrupt.
  The binary value in the timer flip-flops can be
  thought of as a "count" of the number of clock
  pulses (or "events") since the timer was started.

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• There are two 16-bit timers each with four modes
  of operation. A third 16-bit timer with three
  modes of operation is added on the 8052.
• The timers are used for
• (a) interval timing,
• (b) event counting, or
• (c) baud rate generation for the built-in serial
  port.

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• In interval timing applications, a timer is
  programmed to overflow at a regular interval and
  set the timer overflow flag.
• The flag is used to synchronize the program to
  perform an action such as checking the state of
  inputs or sending data to outputs. Other
  applications can use the regular clocking of the
  timer to measure the elapsed time between two
  conditions (e.g., pulse width measurements).

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• Event counting is used to determine the number of
  occurrences of an event, rather than to measure
  the elapsed time between events.
• An "event" is any external stimulus that provides
  a 1-to-0 transition to a pin on the 8051 IC.
• The timers can also provide the baud rate clock
  for the 8051's internal serial port.

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• The 8051 timers are accessed using six special
  function registers.
• An additional five SFRs provide access to the
  third timer in the 8052.

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TIMER MODE REGISTER (TMOD)

• Contains two groups of four bits that set the
  operating mode for Timer 0 and Timer 1
• Not bit-addressable
• Loaded once by software at the beginning of a
  program
• The timer can be stopped, started, and so on by
  accessing the other timer SFRs.

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TIMER CONTROL REGISTER (TCON)

• Contains status and control bits for Timer 0 and
  Timer 1
• The upper four bits in TCON (TCON.4-TCON.7) are
  used to turn the timers on and off (TR0, TR1), or
  to signal a timer overflow (TF0, TF1).
• The lower four bits in TCON (TCON.0-TCON.3) are
  used to detect and initiate external interrupts.

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TIMER MODES AND THE OVERFLOW FLAG

• 13-Bit Timer Mode (Mode 0)
• 16-Bit Timer Mode (Mode 1)
• 8-Bit Auto-Reload Mode (Mode 2)
• Split Timer Mode (Mode 3)

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13-Bit Timer Mode (Mode 0)

• Mode 0 is a 13-bit timer mode that provides
  compatibility with the 8051's predecessor, the
  8048.
• It is not generally used in new designs.
• The timer high-byte (THx) is cascaded with the
  five least-significant bits of the timer low-byte
  (TLx) to form a 13-bit timer.

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16-Bit Timer Mode (Mode 1)

• A 16-bit timer mode
• The clock is applied to the combined high and low
  timer registers (TLx/THx).
• An overflow occurs on the FFFFH-to-0000H
  transition of the count and sets the timer
  overflow flag.
• Overflow flag is the TFx bit in TCON

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8-Bit Auto-Reload Mode (Mode 2)

• 8-bit auto-reload mode
• The timer low-byte (TLx) operates as an 8-bit
  timer while the timer high-byte (THx) holds a
  reload value.
• When the count overflows from FFH, not only is
  the timer flag set, but the value in THx is
  loaded into TLx.

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Split Timer Mode (Mode 3)

• Mode 3 is the split timer mode and is different
  for each timer.
• Timer 0 in mode 3 is split into two 8-bit timers.
• TL0 and TH0 act as separate timers with overflows
  setting the TF0 and TFI bits respectively.
• Timer 1 is stopped in mode 3 but can be started
  by switching it into one of the other modes. The
  only limitation is that the usual Timer I
  overflow flag, TF1, is not affected by Timer 1
  overflows, since it is connected to TH0.
• The 8051 appears to have a third timer.
• Timer 1 can be turned on and off by switching it
  out of and into its own mode 3. It can still be
  used by the serial port as a baud rate generator,
  or it can be used in any way not requiring
  interrupts.

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CLOCKING SOURCES

• There are two possible clock sources, selected by
  writing to the counter/timer (C/T ) bit in TMOD
  when the timer is initialized.
• One clocking source is used for interval timing,
  the other for event counting.

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Interval Timing

• If C/T 0, continuous timer operation is selected
  and the timer is clocked from the on-chip
  oscillator.
• A divide-by-12 stage is added to reduce the
  clocking frequency to a value reasonable for most
  applications.
• The timer registers (TLx/THx) increment at a rate
  of 1/12th the frequency of the on-chip
  oscillator
• A 12 MHz crystal would yield a clock rate of 1
  MHz.

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Event Counting

• If C/T 1, the timer is clocked from an external
  source.
• In most applications, this external source
  supplies the timer with a pulse upon the
  occurrence of an "event" - the timer is event
  counting.
• The number of events is determined in software by
  reading the timer registers TLx/THx
• Port 3 bit 4 (P3.4) serves as the external
  clocking input for Timer 0 and is known as "TO"
  in this context. P3.5, or "T1," is the clocking
  input for Timer 1.

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• The timer registers are incremented in response
  to a 1-to-0 transition at the external input, Tx
• The external input is sampled during S5P2 of
  every machine cycle thus, when the input shows a
  high in one cycle and a low in the next, the
  count is incremented.
• The new value appears in the timer registers
  during S3P1 of the cycle following the one in
  which the transition is detected.
• Since it takes two machine cycles (2 µs) to
  recognize a 1-to-0 transition, the maximum
  external frequency is 500 kHz (assuming 12 MHz
  operation).

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STARTING, STOPPING, AND CONTROLLING THE TIMERS

• The simplest method for starting and stopping the
  timers is with the run-control bit, TRx, in TCON.
• TRx is clear after a system reset thus, the
  timers are disabled (stopped) by default.
• TRx is in the bit-addressable register TCON

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• Another method for controlling the timers is with
  the GATE bit in TMOD and the external input INTx.
• Setting GATE 1 allows the timer to be
  controlled by INTx.
• This is useful for pulse width measurements.
• Assume INT0 is low but pulses high for a period
  of time to be measured.
• Initialize Timer 0 for mode 2, 16-bit timer mode,
  with TL0/TH0 0000H, GATE 1, and TR0 1.
• When INT0 goes high, the timer is "gated on" and
  is clocked at a rate of 1 MHz.
• When INT0 goes low, the timer is "gated off" and
  the duration of the pulse in microseconds is the
  count in TL0/TH0.
• INT0 can be programmed to generate an interrupt
  when it returns low.

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INITIALIZING AND ACCESSING TIMER REGISTERS

• Timers are usually initialized once at the
  beginning of a program
• Within the body of a program, the timers are
  started, stopped, flag bits tested and cleared,
  timer registers read or updated, and so on
• TMOD is the first register initialized
• Timer does not actually begin timing until its
  run control bit, TRx, is set
• If an initial count is necessary, the timer
  registers TL1/TH1 must also be initialized
• 100 µs interval could be timed by initializing
  TLl/TH1 to 100 counts less than 0000H. The
  correct value is -100 or FF9CH.
• Timer is then started by setting the run control
  bit
• Software can sit in a "wait loop" using a
  conditional branch instruction that returns to
  itself as long as the overflow flag is not set
• WAIT JNB TFl, WAIT
• When the timer overflows, it is necessary to stop
  the timer and clear the overflow flag in
  software
• CLR TR1
• CLR TF1

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Reading a Timer on the Fly

• Potential problem that is simple to guard against
  in software.
• Since two timer registers must be read, a "phase
  error" may occur if the low-byte overflows into
  the high-byte between the two read operations.
• The solution is to read the high-byte first, then
  the low-byte, and then read the high-byte again.
• AGAIN MOV A, TH1
• MOV R6, TL1
• CJNE A, TH1, AGAIN
• MOV R7, A

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SHORT INTERVALS AND LONG INTERVALS

• The shortest possible interval is limited, not by
  the timer clock frequency, but by software.
• Presumably, something must occur at regular
  intervals, and it is the duration of instructions
  that limit this for very short intervals.

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• Moderate-length intervals are easily obtained
  using 8-bit auto-reload mode, mode 2. Since the
  timed interval is set by an 8-bit count, the
  longest possible interval before overflow is 28
  256 µs.

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• Timed intervals longer than 256 µs must use
  16-bit timer mode, mode 1. The longest delay is
  216 65,536 µs or about 0.066 seconds. The
  inconvenience of mode 1 is that the timer
  registers must be reinitialized after each
  overflow, whereas reloading is automatic in mode
  2.

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• Intervals longer than 0.066 seconds can be
  achieved by cascading Timer 0 and Timer 1 through
  software, but this ties up both timers. A more
  practical approach uses one of the timers in
  16-bit mode with a software loop counting
  overflows. The desired operation is performed
  every n overflows.

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8052 TIMER 2

• Five extra special-function registers are added
  to accommodate Timer 2.
• The timer registers, TL2 and TH2
• The timer control register, T2CON
• The capture registers, RCAP2L and RCAP2H.
• Can operate as an interval timer or event
  counter.
• The clocking source is provided internally by the
  on-chip oscillator, or externally by T2, the
  alternate function of Port 1 bit 0 (P1.0)
• Three modes of operation auto-reload, capture,
  and baud rate generator.

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Auto-Reload Mode

• CP/RL2 0
• TL2/TH2 are the timer registers, and
  RCAP2L/RCAP2H hold the reload value
• Timer 2 is always a full 16-bit timer, even in
  auto-reload mode.
• Reload occurs on an FFFFH-to-0000H transition in
  TL2/TH2 and sets the Timer 2 flag, TF2. This
  condition is determined by software or is
  programmed to generate an interrupt. Either way,
  TF2 must be cleared by software before it is set
  again.
• By setting EXEN2 in T2CON, a reload also occurs
  on the 1-to-0 transition of the signal applied to
  pin T2EX (P1.1)
• A 1-to-0 transition on T2EX also sets a new flag
  bit in Timer 2, EXF2.
• EXF2 is tested by software or generates an
  interrupt. EXF2 must be cleared by software.

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Capture Mode

• CP/RL2 1
• The TF2 bit set upon an FFFFH-to-0000H transition
  of the value in TL2/TH2. The state of TF2 is
  tested by software or generates an interrupt.
• To enable the capture feature, the EXEN2 bit in
  T2CON must be set.
• If EXEN2 1, a 1-to-0 transition on T2EX (P1.1)
  "captures" the value in timer registers TL2/TH2
  by clocking it into registers RCAP2L and RCAP2H.
  The EXF2 flag in T2CON is also set and, as stated
  above, is tested by software or generates an
  interrupt.

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BAUD RATE GENERATION

• Another use of the timers is to provide the baud
  rate clock for the on-chip serial port.
• This comes by way of Timer 1 on the 8051 IC or
  Timer 1 and/or Timer 2 on the 8052 IC.