Title: EE4271 VLSI Design
1EE4271 VLSI Design
Dr. Shiyan Hu Office EERC 518 shiyan_at_mtu.edu
The Inverter
Adapted and modified from Digital Integrated
Circuits A Design Perspective by Jan M. Rabaey,
Anantha Chandrakasan, and Borivoje Nikolic.
2Circuit Symbols
3The CMOS Inverter A First Glance
VinVdd,Vout0 Vin0,VoutVdd
4CMOS Inverter - First-Order DC Analysis
5CMOS Inverter Transient Response
V
V
DD
DD
Delay0.69RC
R
p
V
V
out
out
C
C
L
L
R
n
V
V
V
0
in
DD
in
(a) Low-to-high
(b) High-to-low
6NMOS In Inverter
- For NMOS
- Vin0, Vgsn0ltVtn, VdsnVoutVdd, NMOS is in
cut-off region, X1. - PMOS is on. VoutVdd.
- VinVdd, instantaneously, VgsnVddgtVtn,VdsnVoutV
dd, Vgsn-VtnVdd-VtnltVdd, NMOS is in saturation
region, X2 - Instantaneously, Vgsp0gtVtp. PMOS cut-off
- NMOS is on so Vdsn-gt0. The operating point
follows the arrow to the origin. Vout0 at X3.
7The CMOS Inverter
Assume that Idsp-Idsn when both transistors are
on and VtnVtp
8The CMOS Inverter 2 (Region A)
0ltVinltVtn
VgspVin-VddgtVtp, VdspVd-Vdd0ltVgsp-Vt
p PMOS linear region
S
D
Vd is close to Vdd
D
S
VgsnVinltVtn, NMOS cut-off
9The CMOS Inverter 3(Region B)
VtnltVinltVdd/2
VgspVin-VddgtVdd/2gtVtp, Vdsp0ltVgsp-Vtp
PMOS linear region
S
D
D
S
VgsnVingtVtn, VdsnVoutVddgtVgsn-Vtn NMOS
saturation region
10The CMOS Inverter - 4
11The CMOS Inverter 5(Region C)
VinVdd/2
VgspVin-VddgtVtp, VdspgtVgsp-Vtp,
saturation
S
D
D
S
VgsngtVtn, VdsngtVgsn-Vtn, saturation
12The CMOS Inverter - 6
Usually,
Usually we set for equal rising
and falling propagation delay (same R for both
devices)
13The CMOS Inverter 7
- VinVoutVdd/2
- The above analysis is actually correct for
Vinvdd/2 and all Vout such that both devices are
in saturation regions - For NMOS, VoutgtVin-Vtn
- For PMOS, Vgsp-VtpgtVdsp -gtVoutltVin-Vtp
- Vin-VtnltVoutltVin-Vtp, so for VinVdd/2, Vout can
vary around Vdd/2
14The CMOS Inverter 9(Region D)
Vdd/2ltVinltVdd-Vtp
VgspVin-VddgtVtp, VdspVd-VddgtVgsp-Vtp
, PMOS saturation region
S
D
D
S
VgsnVingtVtn, VdsnVoutltVgsn-Vtn NMOS linear
region
15The CMOS Inverter - 10
16The CMOS Inverter 11(Region E)
VingtVdd-Vtp
VgspVin-VddltVtp, PMOS cut-off
S
D
D
S
VgsnVingtVtn, VdsnltVgsn-Vtn NMOS linear
17The CMOS Inverter -12
18The CMOS Inverter
19Circuit Under Design
20Its Layout View