Prabhat Mishra HeonMo Koo Zhuo Huang - PowerPoint PPT Presentation

Title: Prabhat Mishra HeonMo Koo Zhuo Huang


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Language-driven Validation of Pipelined
Processors using Satisfiability Solvers

• Prabhat Mishra Heon-Mo Koo Zhuo
  Huang
• Department of Computer and Information Science
  and Engineering
• University of Florida
• MTV 2005

2
Outline

• Introduction
• Traditional Validation Approaches
• Language-driven Validation
• Top-Down Validation using SAT solvers
• Test Generation
• Equivalence Checking
• Summary

3
Technology and Demand
of transistors are doubling every 2 years
Demand
Technology
Communication, multimedia, entertainment,
networking
Exponential growth of design complexity ?
verification complexity
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Validation of Pipelined Processors

• Functional validation is a major bottleneck
• Deeply pipelined complex micro-architectures
• Logic bugs increase at 3-4 times/generation
• Bugs increase (exponential) is linear with design
  complexity growth.

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Outline

• Introduction
• Traditional Validation Approaches
• Language-driven Validation
• Top-Down Validation using SAT solvers
• Test Generation
• Equivalence Checking
• Summary

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Traditional Validation Approach
Architecture Specification (English Document)
RTL Design
Simulation
7
Traditional Validation Approach
Architecture Specification (English Document)
Model Checking
Abstracted Design
Abstraction
RTL Design
Simulation
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Traditional Validation Approach
Architecture Specification (English Document)
Specification
Model Checking
Verification
Formal
Abstracted Design
Implementation
Abstraction
RTL Design
Simulation
9
Traditional Validation Approach
Architecture Specification (English Document)
Analysis/Verification
Specification
Specification
Model Checking
Verification
Formal
Abstracted Design
Implementation
Abstraction
RTL Design
Simulation
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Traditional Validation Approach
Architecture Specification (English Document)
Analysis/Verification
Specification
Specification
Model Checking
Verification
Formal
Abstracted Design
Implementation
Abstraction
Transform
RTL Design
Modified Design (RTL / Gate)
Simulation
Equivalence Checking
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Traditional Validation Approach
Architecture Specification (English Document)
Analysis/Verification
Specification
Specification
Model Checking
Verification
Formal
Abstracted Design
Implementation
Design Reference Models
Abstraction
Implementation
Transform
RTL Design
Modified Design (RTL / Gate)
Simulation
Equivalence Checking
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Outline

• Introduction
• Traditional Validation Approaches
• Language-driven Validation
• Top-Down Validation using SAT solvers
• Test Generation
• Equivalence Checking
• Summary

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Top-down Validation Methodology
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Top-down Validation Methodology
ADL Architecture Description Language
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Top-down Validation Methodology
ADL Architecture Description Language
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Top-down Validation Methodology
http//www.ics.uci.edu/express
HDL Description
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Top-down Validation Methodology
Design Validation
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Top-down Validation Methodology
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Language-driven Validation
Architecture Specification
Processor Core
Memory Subsystem
Coprocessors
ADL Specification
Test Vectors
Simulator
RTL Design (Implementation)
Check Output
HDL Description
Equivalence Checking
Fail
Fail
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Language-driven Validation
Architecture Specification
Processor Core
Memory Subsystem
Coprocessors
ADL Specification
Test Vectors
Simulator
SATBDDATPG ?
RTL Design (Implementation)
Check Output
HDL Description
Equivalence Checking
Fail
Fail
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Outline

• Introduction
• Traditional Validation Approaches
• Language-driven Validation
• Top-Down Validation using SAT solvers
• Specification using Architecture Description
  Language
• Test Generation
• Equivalence Checking
• Summary

22
Architecture Description Languages

• Behavior-Centric ADLs
• ISPS, nML, ISDL, SCP/ValenC, ...
• primarily capture Instruction Set (IS)
• good for regular architectures, provides
  programmers view
• tedious for irregular architectures, hard to
  specify pipelining
• Structure-Centric ADLs
• MIMOLA, ...
• primarily capture architectural structure
• specify pipelining drive code generation, arch.
  synthesis
• hard to extract IS view
• Mixed-Level ADLs
• LISA, RADL, FLEXWARE, MDes, EXPRESSION,
• combine benefits of both
• generate simulator and/or compiler

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Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
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Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
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Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
26
Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
27
Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode P7 C4 P8) (WB RF P5 C3
P6) ) (TYPE BI (MEM MEMORY P4 C2 P3) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
28
Specification of the DLX Processor
PC
Memory
Fetch
Structure
( ARCHITECTURE_SECTION ..........
(FetchUnit Fetch (CAPACITY 4) (TIMING (all
1)) (OPCODES all) (LATCHES (OTHER
PCLatch)(OUT DLatch)) ) ( PIPELINE_SECTION
(PIPELINE Fetch Decode Execute MEM WB) (Execute
(ALTERNATE ALU MUL FADD DIV)) (FADD (PIPELINE
FADD1 .. FADD3 FADD4)) (DTPATHS (TYPE
UNI (RF Decode) (WB RF) ) (TYPE
BI (MEM MEMORY) ) )
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
FADD3
FADD4
MUL7
MEM
WriteBack
29
Specification of the DLX Processor
Structure
PC
Memory
Fetch
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
Behavior
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
FADD3
FADD4
MUL7
MEM
WriteBack
30
Specification of the DLX Processor
Structure
PC
Memory
Fetch
Decode
Register File
DIV
FADD1
IALU
MUL1
FADD2
MUL2
Behavior
Mapping
(OPCODE ADD (OPERANDS (SRC1 rf) (SRC2 imm)
(DEST rf)) (BEHAVIOR DEST SRC1 SRC2)
(FORMAT ) )
FADD3
FADD4
MUL7
MEM
WriteBack
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Outline

• Introduction
• Traditional Validation Approaches
• Language-driven Validation
• Top-Down Validation using SAT solvers
• Test Generation
• Equivalence Checking
• Summary

32
Functional Verification of Pipelined Processors
Test Generator
Pipelined Processor
TestGen
MOV R1, 011 MOV R2, 010 ADD R3, R1, R2 R3 101
Test Program
R3 101 ?
Check Result
Verify the functionality of the processor using
assembly programs
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Related Work

• Directed test program generation
• Aharon et al., DAC 1995, Shen et al., DAC 1999
• Test generation for pipelined processors
• Ur and Yadin, DAC 1999
• Iwashita et al., ICCAD 1994
• Campenhout et al., DAC 1999
• Mishra et al., DATE 2005
• Functional test program generation
• Chen et al., DAC03, Lai and Cheng, DAC01
• Thatte et al., IEEE Computers, 1980
• Applied in the context of manufacturing testing

34
Test Generation Methodology
Architecture Specification
ADL Specification
Simulator Generation
SMV
Not Enough Properties
Counterexamples
Coverage Report
Simulator
Automatic
ADL Architecture Description Language
Manual
Test Programs
Feedback
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Modified Test Generation Methodology
SMV Description (for node N)
Property (for node N)
SMV
N parent of N
N parent of N
Counterexamples
input assignments
primary i/p?
output req. for parent node
yes
Simulator
coverage report
test programs
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Test Generation Results

• VLIW DLX Processor
• Test Generation Techniques
• SMV Model Checker
• SMV bmc using zChaff SAT solver

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Outline

• Introduction
• Traditional Validation Approaches
• Language-driven Validation
• Top-Down Validation using SAT solvers
• Test Generation
• Equivalence Checking
• Summary

38
Challenges in Top-Down Validation
Architecture Specification
Processor Core
Memory Subsystem
Coprocessors
ADL Specification
TestGen
Test Vectors
Simulator
RTL Design (Implementation)
Check Output
HDL Description
Equivalence Checking
Fail
Fail
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Equivalence Checking

• Simple processor model
• Simple 5-stage pipeline
• fetch, decode, read operand, execute, and write
  back
• Four registers and five possible instructions
• NOP, AND, OR,  NOT, and LOAD
• UCSB Seq_SAT, Sequential SAT Solver
• Run Time 1.8 seconds
• 18 inputs, 1 output, 267 gates and 98 DFFs

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Summary

• Functional verification is a major challenge
• Top-down validation a promising approach
• Processor specification using ADL
• ADL-driven functional validation
• Challenges in language-driven validation
• Test generation
• Equivalence checking
• Initial results on using SAT solvers in the flow
• Future work
• Further exploration of existing SAT based flows
• Development of application-specific SAT solvers

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• Thanks!

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Pentium 4 Bugs Breakdown
Source Bob Bentley, HLDVT 2002
Micro-architectural complexity is a major
contributor