Abstract

1
Abstract

• To test integration efforts of the BEE and SSHAFT
  design flows, a model channel decoder based on
  the BCJR algorithm was designed and simulated on
  the BEE board. Hardware simulations have made it
  easier for communications engineers to expedite
  the testing of algorithms.

2
Goals

• Pipe cleaning exercise for the current SSHAFT
  flow as we move into 130nm and future process
  technologies
• Generate waterfall curves (BER vs. SNR)
  quickly.
• Or more specifically, move as much as we can on
  the FPGA

3
System Design and Testbed

• Comprehensive utilization of System Generator
  blockset
• Addsub, register, counter, accumulator, single
  port RAM, ROM, etc
• 10 MHz system clock
• SNR 14db ? -1db
• 109 Samples
• Parameterized to support variable binary point
  precision, SNR, number of samples

4
System Architecture

• E2PR4 Channel Encoder - Decoder
• Fully enclosed design
• Uniform RNG input vector
• Channel encoder
• AWGN filter
• Channel decoder
• BER collection mechanism
• Part of Full 3G Turbo Decoder

5
Simulation Techniques

• On-chip signal and noise generators
• Hardware-based uniform RNG based on cellular
  automata
• Additive white Gaussian noise derived from same
  uniform RNG
• Easy to hard-code and control SNR in FPGA

6
Applications

• Functional Evaluation
• Will the design work in hardware? Find out by
  testing it on BEE board
• Performance Evaluation
• Bit-Error Rate (BER), etc..
• Would another algorithm perform better?
• Design Reusability
• More robust library elements and building blocks
  are available for future designs, all based on
  Xilinx blockset and derivatives

7
Simulation Results
10MHz, 109 Samples, 1 bit binary point
precision Runtime approx. 30 minutes
8
In the works

• Modified design to incorporate encoder/decoder
  for 3G wireless systems
• First pass of original design into ASIC-based
  SSHAFT backend flow
• Methdology to increase highest possible clock
  rate for simulated system
• Current design is limited to 10MHz system clock
  due to long logic paths.

9
Looking forward

• What can we expect to see at the next retreat?
• Chips, chips, and more chips!
• A fully integrated SSHAFT/BEE design flow with a
  complete library of primitives and reusable
  blocks for newer designs