Circuit Performance Variability Decomposition

1

• Circuit Performance Variability Decomposition
• Michael Orshansky, Costas Spanos, and Chenming Hu
  
• Department of Electrical Engineering and
  Computer Sciences, University of California at
  Berkeley

2
Overview

• Motivation need to know sources of circuit
  variability
• New considerations
• Increasing role of interconnect
• Importance of intra-field variability
• Variability modeling
• Critical path circuit
• Analytic delay calculation
• Realistic linewidth variation model
• Analysis of modeling results
• Conclusions

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Circuit Performance Variability Decomposition
Motivation

• Causal decomposition to find major sources of
  variability
• Designing for reduced sensitivity
• Reducing the amount of statistical information
• Reducing the simulation effort by scaling
  statistical input space dimensionality
• Maximizing yield more accurate limits of
  acceptable parameter spreads
• Emphasis in this project device vs interconnect
  variability decomposition

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New Considerations Interconnect

• Traditionally device variability is dominant
• Deep Sub-Micron interconnect delay contribution
  grows
• Perhaps interconnect variability dominates
• Realistic analysis has to consider device and
  interconnect variability jointly
• Need to distinguish global and local interconnect
• Average wirelength of local (lower level) metal
  lines scales down as gate length is reduced
• Global (higher level) lines become longer as the
  chip size increases

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New Considerations Within-Field Variability

• Traditionally between-field variability is
  dominant
• Deep Sub-Micron within-field gate CD variability
  is significant
• Within-field variability is deterministic
• Can be treated as random for simplicity

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Critical Path Circuit

• Need a representative circuit for high-speed CMOS
  designs such as microprocessor
• Critical path circuit
• 14-stage gate chain
• 2-input NANDs with average FO2.5
• Gate stages separated by local interconnect lines
• There is one global interconnect line buffered by
  repeaters

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Analytic Delay Modeling

• Sakurais delay model D0.4RwCw0.7(RdClRdCwRwC
  l)
• Device behavior RdVdd/Id
• We also use Sakurais analytical 2-D capacitance
  models

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Variability Modeling

• Variability model
• Assume linear delay response
• Variability of each source is
• Improved model of global interconnect linewidth
  variation
• This model predicts smaller variability of
  effective W in global lines

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Impact of Technological and Circuit Choices A
Case Study of 0.18um Technology

• Can define . Decomposition depends on
• Technology parameters (nominal and statistical)
• Circuit characteristics (typical)
• Case study Lgate0.18
• Device Parameters Tox40A, Vdd1.8V
• Current drive Id(Lg)0.56mA-1.9(Lg-0.18)
• Interconnect Parameters

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Sensitivity of Delay to Local Interconnect

• Sensitivity is
• Sensitivity to gate CD is highest and still
  increases in this range
• Conditions Lglobal1.15 cm

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Sensitivity of Delay to Global Interconnect

• At large Lglobal sensitivity to Wg and Tg is
  comparable to Lgate
• Increase of sensitivity due to Wg and Tg is
  drastic for small pitch
• Conditions , 3 repeaters
  used

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Effect of Buffering on Delay Sensitivity

• Increasing the number of repeaters by 2
  reduces sensitivity to global interconnect
  parameters Wg and Tg by 30
• Use of repeaters both reduces delay and delay
  sensitivity

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Effect of Reducing Metal Pitch

• Sensitivity to global parameters drastically
  increases for smaller pitches
• Sensitivity to Lgate is still highest
  (Lglobal1.15cm)

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Improved Interconnect Variability Model

• Model predicts reduction of and
  increase of sensitivity with Lglobal
• Consider a buffer driving a line with no
  repeaters and
• At large Lglobal, delay variability due to Wg
  is strongly attenuated

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Variability Decomposition an Example

• Need to assume specific variance values
• Values depend on design/technology choices
• good design wide pitch for global
  interconnect, min pitch for local connections
• Assumed max (3-sigma) parameter deviations
  (normalized)

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Variability Decomposition Results

• Only for poor designs, a sizable portion of
  variability (35) is due to interconnect
• For good designs interconnect variability
  contribution is small (12)
• Improved model accounts for reduction of
  in large Lglobal

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Summary and Conclusions

• Analytical circuit performance variability
  decomposition proposed to assess interconnect and
  device contributions
• Need to consider device and interconnect
  variability jointly
• Exact decomposition is specific for circuit and
  technology
• Optimal designs lead to better performance and
  smaller interconnect variability contribution
• Use of repeaters leads to reduction of
  interconnect contribution
• Device variability remains the dominant source of
  overall variability in circuit performance (about
  90)