Realtime Systems

1
Real-time Systems

• Definitions
• Event Any occurrence that causes the program
  counter to change non-sequentially is considered
  a change of flow control, and thus an event.
• Signal Anything that can generate an event
• A variable changing from non-zero to zero
• An input level or transition
• A variable exceeding a specified value
• A timer rolling over

2

• Definitions, continued
• The time between the presentation of a set of
  inputs and the associated output is called the
  response time of a software system.
• A real-time system is (1) A system that must
  satisfy explicit (bounded) time response
  constraints or risk severe consequences, possibly
  total failure. (2) Logical correctness is based
  upon both correct state and during the specified
  time.
• A failed system is one that cannot satisfy one or
  more of the requirements stipulated in the formal
  system specification.

3

• Definitions, continued
• Determinism A system is said to be deterministic
  if, for each possible state and each set of
  inputs, a unique set of outputs and states can be
  determined.
• Time Loading or utilization factor is a measure
  of useful processing the computer is doing.
• Soft real-time system A system in which failing
  to meet time-response requirements constitutes a
  performance degradation but is not considered a
  system failure.
• Hard real-time system A system in which failing
  to meet any response time requirements
  constitutes a system failure.
• Firm real-time systems Systems that have a low
  probability of failing to meet response time
  requirements

4
Event Generation

• Polled software loop that samples signals
• Interrupt hardware logic that forces an event
  in response to a signal
• Which to use? Depends upon signal
  characteristics
• Signal characteristics
• Time Persistence and frequency
• Logic State and transition (edge triggered)

5
More definitions

• Latency The time from when a signal becomes
  active and the computer begins processing the
  signal.
• Context the minimum information that is needed
  to be saved for a currently executing task so
  that it can be resumed.
• Context Switching the process of saving and
  restoring sufficient information for a real time
  task so that it can be resumed after an interrupt.

6
More definitions

• Background Non-interrupt driven processes in a
  foreground / background system
• Foreground A collection of interrupt driven or
  real-time processes. Foreground processes are
  preemptive and have higher priority (access to
  CPU time) than background systems
• Protected code is code that must not be preempted
  to avoid high probability of system failure.

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Event Generation by Polling

• Polling is done repeatedly in a software loop.
• Maximum Latency is determined
• System loading is maximum
• All events must be processed in a single loop
• Maximum execution time for all processes
• The time until the inputs are polled again
  assuming that the signal became active
  immediately after polling.

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Event Generation by Polling

• Signal persistence is required to be longer than
  the maximum latency
• Signal frequency must be less than the inverse of
  the maximum latency plus the specific event
  processing time.
• Maintains system determinism
• Requires no context switching
• Simple to implement (HW SW)

9
Interrupts

• Preempt code execution
• Requires context switching
• Destroys system determinism
• Requires special CPU hardware
• Difficult to manage unless limited in number
• Lower latency (but not zero)
• Lower persistence requirements
• Can be prioritized

10
Interrupts

• How they work
• Signal becomes active
• Hardware latches indication
• CPU finishes executing current instruction
  (assembler) and, for some processors, the
  following instruction also.
• Saves the address of the next instruction
• Executes an absolute call instruction to the
  start interrupt service routine (ISR).
• Saves the necessary context
• Executes code in the ISR
• Restores the context
• Returns to the saved address

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Types of Interrupts

• Fully Vectored Interrupts
• Each interrupt input has a unique address that is
  called for the ISR
• Polled Interrupts
• One vectored address and multiple interrupts must
  be parsed out by polling status or reading a
  cause register
• Mixed Systems
• Combination of both Fully Vectored and Polled
  Interrupts. E.g. dedicate timer system interrupt,
  but poll for specific timer.

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Interrupts Latency

• Latency is determined by
• Instruction time (how long is the longest)
• How much of the context must be saved
• How much of the context must be restored
• The effort to implement priority scheme
• Time spend executing protected code

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Interrupts Latency no-nesting
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Interrupts Latency
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Interrupts Latency full nesting
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Interrupts Latency nested

As a rule of thumb, Z-World usually suggests that
100 µs be allowed for interrupt latency on Z180-
or Rabbit-based controllers.
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Privilege and Atomic Instructions

• Privilege means that an interrupt cannot take
  place between the privileged instruction and the
  following instruction.
• The instructions to modify the IP register are
  privileged
• To avoid disabling interrupts while copying a
  shadow register to its target register, it is
  desirable to have an atomic move from memory to
  I/O space. (LDD and LDI) instructions.