Interrupts

1
Interrupts

• We have looked at two I/O models
• Asynchronous read/write at will
• Polled watch a status bit and wait for data
  to be available, then read/write data
• Clearly, polling is necessary in many cases, but
  it is inefficient
• Might want to do something else while waiting for
  status bit to change
• Difficult when polling many different peripherals
• Interrupts offer a solution
• Peripheral issues an interrupt
• Processor finishes what it was doing, then
  executes a special subroutine to handle interrupt
• Processor returns to what it was doing before
  interrupt.

2
An Analogy - Waiting for a Package

• Read a page
• Go to door to see if package is there
• If so, grab package, open, and use contents.
• Go back and read another page of book
• Do you get package as soon as it arrives?
• Do you know when you will finish book?

• Read
• When doorbell rings
• Finish sentence
• Place bookmark
• Go to door get package
• Process or set aside
• Return to couch
• Open book to bookmark
• Continue reading

3
In General

• Main program runs
• Interrupt occurs
• Instruction finishes
• All registers pushed to stack
• All other interrupts disabled
• Determine source
• Lookup destination (vector)
• Execute interrupts service routine (at vector)
• When finished, issue RTI (return from interrupt)
• Main program resumes

4
On HC11

• Interrupts can occur after any instruction
• Instruction allowed to finish
• Most instructions 2 7 cycles
• FDIV/IDIV 41 cycles
• All registers are stacked automatically
• Less predicable than subroutine
• Cannot really pass parameters to ISR
• about 14 clock cycles
• Other interrupts are disabled (I bit in CCR)
• Processor determines highest priority source
• HC11 has 18 interrupt sources

5
Interrupt Latency

• Latency the amount of time that it can take the
  processor to respond to an interrupt.
• Depends on instruction executing when interrupt
  issued
• 2 41 cycles (1 to 20.5 us)
• Stacking registers
• 12 cycles ( 6 us)

6
Stacking Registers
SP after interrupt
SP before interrupt
7
Interrupt Vectors

• In Pink Book (normal mode)
• FFD6 SCI
• FFF2 IRQ
• If system has RAM at these locations we can write
  these vectors (development)
• If system has ROM we may be able to write these
  (deployment)

8
Jump Table

• If using Buffalo boot ROM, often re-vector to
  page 0, which is always RAM
• We would need to install a short subroutine there
  to jump to real ISR
• Example

9
Enabling Interrupts

• Interrupts from onboard peripherals are visible
  based on the I (interrupt mask bit) bit in CCR
• CLI allows interrupts to occur
• SEI turns off interrupts
• I bit is set (interrupts masked) during an
  interrupt so another interrupt does not interrupt.

10
HC11 Peripherals

• Most HC11 subsystems (timers, etc.) require
  additional handling
• Enable peripheral to interrupt
• Enable interrupts (CLI)

11
Testing Interrupts

• SWI software interrupt
• Calls ISR at vector
• Convenient

12

• _start lds _stack good practice
• This example is for BUFFALO montior which
  redirects interrupt vectors
• to a jump table in Page 0 RAM. Wytec users can
  write the interrupt vector
• directly
• ldx 0xFFEA load location of Page0 jump
  vector - FFEA is normal vector for IC3
• ldaa 0x7E load jmp instruction into ACCA
• staa 0,x store jmp instruction at jump
  vector
• ldd ISR get address of ISR
• std 1,x store address of ISR at jump vector
• Set up IC3 (PA0) for interrupts
• IC3 is alwas an input, so there is no DDR issue
• ldaa TMSK1 load the Main Timer Interrupt
  Mask Register 1
• oraa 0b00000001 set bit 0 - enable IC3
• staa TMSK1