Circuit Design Environment and Layout Planning

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Circuit Design Environment and Layout Planning

• Bharat Krishna Gil Kleinfeld
• Presented by
• Shai Isaac
• Computer-aided design of VLSI seminar
• By Amir Rahat

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Agenda

• Traditional design flow- how it is done today
  drawbacks
• New methodology
• New design flow
• Benefits ,FCDE tool
• Example speed path design
• Results
• Future work

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Traditional design flow
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Traditional design flow

• Traditional methodology can be described as a
  water fall model, the results of a completed
  stage are passed to the next stage.
• Results at each stage are evaluated without any
  consideration of their effect on later stages
• If results are not satisfying a fix is done in
  the same stage.If still not satisfied it should
  be fixed
• in the previous stage so on.
• Number of iterations can occur.
• Very time consuming costly

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Traditional design flow

• Many tools as a result many different file
  formats
• many converters are needed
• Non - interactive design
• Should maintain data consistency
• Unnecessary task partitioning as a result of
  different tools the inconsistent between them.
• Different tools have inconsistent user interfaces
• In general each stage is done by different
  persons so data should be obtained - obtaining
  data takes time.

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Traditional design flow

• focuses on local optimizations - designers can
  optimize in each stage different aspects and
  different tools are available for them.
• For example in speed path process circuit
  designers tend to optimize the paths using device
  sizing and not by optimizing the interconnect
  delay which is done later.
• Forces early binding
• Decisions at one stage become hard inputs to the
  next stage
• Very difficult to change these input constraints
  later on in the flow

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Traditional design flow

• Long iterations due to return to previous
  stages and because many different engineers would
  be required to run their tools in the required
  order.
• A design is reloaded many times into different
  tools, which significantly slows progress.

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Conclusion

• Interaction between two stages in the flow is
  time consuming,costly and can effect later
  design.
• A new approach should be considered

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A New Methodologyis proposed

• An environment which enables overlapping of
  design stages
• The overlap is enabled by providing easy access
  to multiple tools and by using a common data
  model across multiple domains
• A tool that can manipulate the design data, and
  any changes are available to another application
• Interactive design environment
• What-if glimpse crosses traditional boundaries

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A New Methodologyis proposed cont.

• The price- increases the complexity of tool
  development of linking internal data
  representations

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A New Methodology

• The design stage overlap concept will focus on
  the interaction between the circuit design and
  layout design stages

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New design flow
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A New Methodology

• We will see the benefits of the new approach
• by understanding how the new tool works
• and comparing it to the old approach.

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FCDE

• An integrated, interactive circuit design
  environment that incorporates multiple tools,
  data, constraints, and analysis tools
• FCDE integrates all circuit design tools
  including circuit simulation, layout planning,
  parasitic estimation, timing analysis, circuit
  optimizers

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Workflow diagram circuit and layout interaction
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Layout planner-background

• Repeat iterations are necessary when the final
  layout does not satisfy all the assumptions made
  during the circuit design phase.
• In order to reduce design iterations it is
  necessary to use layout information (e.g.,
  interconnect delays) during the circuit design
  stage
• In the new approach the circuit and layout
  planning will be done in parallel
• The layout planner is a very important component
  of the circuit design environment.
• Later we will complete the remaining of layout
  work

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Layout Planner

• The layout planner provides functionality to
  estimate area and interconnect parasitic
• Also allows the user to accomplish some layout
  tasks earlier. such as global routing, congestion
  analysis etc.
• This will help later to reduce the layout design
  effort significantly

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Layout Planner

• The layout-based estimates are used during the
  circuit design stage to carry out more accurate
  circuit simulations
• Layout planning flow is developed from experience
  with prototypes used in some recent
  microprocessor design projects
• The layout planning flow provides various
  trade-off points so that the circuit designer can
  get better estimates on interconnect design at
  the cost of tool performance.

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Functionality

• The inputs to the layout planning tool are design
  constraints, user-defined placement hints, and
  the netlist (which may be incomplete).
• The user can visually see and edit the placement
  and change the netlist
• Higher drive strength requirements, or any other
  interconnect optimization done will modify the
  netlist if a cell used in the block is changed

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Placement Modeling

• In datapath layout planing we want to change,
  move, delete, create cells and see how it effects
  the unit.
• Multiple instantiations of logic cells are common
  in datapath blocks
• It will be more efficient if same actions on same
  kinds of cells will be done only once.
• By the layout planner multiple instances of a
  cell are grouped into entities known as vectors
• The complete layout plan is modeled as a matrix
• Layout editing provides a means to edit groups of
  instances in one command.
• The tool then provides commands to move, delete,
  create vectors, rows, matrices, etc.

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Parasitic estimation Optimization

• During layout planning the design engineers need
  to estimate the interconnect delays.
• Interconnect delaysparasitic resistance
  capacitance. It depends on the interconnect
  length
• Up until now two methods were used circuit
  estimate detailed routing.

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Parasitic estimation Optimization

• Circuit estimate
• By analyzing the logic of interconnect.
• for example If we have a design divided into sub
  blocks, which are divided into smaller
  subsubblocks, then we can estimate that a signal
  that goes from one subsubblock to another (which
  is inside a different block) will require a long
  route, compared to a signal that stays in the
  same subsubblock.
• Short in time but rough in estimate
• Detailed routing
• Very accurate but could take months .. ?.

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Interconnect Estimation Optimization cont.

• Additional 2 estimation algorithms were added to
  the layout planner based on the placement
• the Steiner tree
• connects points using Manhattan routes.
• This estimation generates optimistic net lengths
• Quick runtime but no consideration is given to
  obstructions or congestion
• global routing
• selects which quadrants the route will go
  through.
• Global routing accounts for obstructions as well
  as congestion
• Considers physical net specifications (width,
  spacing).
• This option for net length estimation is slower
  than the Steiner estimation

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Cont. Interconnect Estimation and Optimization

• The order of these algorithms by parameters of
  time and estimation accurately (From less
  accurate and fast to more accurate and slow)
• Circuit estimate
• Steiner alg
• Global routing
• Detailed routing
• The layout planning tool allow the user to make
  tradeoffs between runtime and accuracy of the
  estimates.

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Track Share Analysis

• After a reasonable placement was determined the
  user is able to estimate interconnect parasitics
• The location of the interface ports of the cell
  can also be planned to enable better routing (see
  in the figure)
• Gives the designer control of top-down as well as
  bottom-up of datapath block layout design thanks
  to the interconnect parasitics estimate.

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Track Share Analysis
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Visualization

• Based on the congestion analysis, the user can
  manually adjust the placement
• The tool provides net visualization and editing
  functionality to interactively optimize the
  interconnect delay
• FCDE provides path viewing including path
  properties (start point, end-point,etc.) and
  debugging capabilities for speed-path analysis
  and optimization

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Incremental Design mode

• Convenient for what-if analysis work
• For example the user may want to change the
  placement of a few instances and see how the area
  or timing on those affected nets has changed
• The tool re-computes the desired properties for
  the effected nets only and also can display the
  delta changes.
• In order to enable interactive design the timing
  analysis engine is quick (but rough)

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Cell Area Estimation

• Reminder layout planning happens before any real
  layout is created
• Planner is to be able to estimate cell area from
  the netlist of the cell
• The first method is to use a statistically
  derived equation for estimating cell area in
  general depends on the number of devices I/O
  ports
• Second method is to use historical data

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Noise Analysis

• Important to account for noise as the operating
  voltage for deep sub-micron design is decreasing,
  and the noise effect is becoming more visible
• Currently the layout planner provides a means to
  visualize the noise as aggressor-victim pairs .
• Current experimental work is directed towards
  auto identification of aggressors and victims

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Noise Analysis

• Noise analysis involves information that is
  spread across both the circuit design and layout
  design stages
• As both of these stages are tightly integrated in
  the new design flow, all the information required
  for noise analysis is available simultaneously.

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Device Size Tuning

• Device size tuning is needed if we want to change
  the device strength (increase cell size will
  improve speed , decrease cell size will save area
  or power)
• FCDE will enable circuit designers to change the
  size of a device or a cell in the schematic
  editor or in one of the FCDE viewers
• The change will be applied on the FCDE data
  model, and incremental analysis will be made to
  analyze this change

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An example Speed-Path Design

• The advantages of the proposed system as it used
  on the speed-path design activity
• Speed path debug is done when we have violating
  paths.
• This design activity encompasses both circuit
  design and layout design. It uses several tools
  and various types of data in both of the design
  domains

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Speed path optimization flow
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Speed-Path Design cont.

• The designer runs tools to identify critical
  paths
• To optimize the paths with violations, there are
  multiple possibilities
• Increase the driver strength
• Reduce the driver load
• Optimize the interconnect loading
• The first two options are handled by the
  device-sizing functionality in circuit design,
  and the last one is carried out in layout design.

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Old methodology

• With current tools, all these activities are
  carried out by different tools , data is
  exchanged by means of files , multiple design
  engineers involved.
• Since data files are used, it is difficult to
  exchange partial data.
• It takes in the order of weeks to optimize a path
  if accurate interconnect loading is to be
  obtained

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Old methodology

• The reasons for the long turn-around time are
• Layout design is carried out by a different
  person and the turn-around time for obtaining
  data is long
• Layout design has to be completed before data is
  obtained, and data interfacing is difficult Thus
• Circuit designers tend to optimize the paths
  using device sizing and do not explore all
  possible solutions (such as optimizing the
  interconnect delay).

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New methodology

• With the new integrated design environment
• The interconnects can be optimized as easily as
  devices can be sized
• All the different tools are accessible via a
  common user interface
• Since all the tools are working with the same
  data model, the data is exchanged in memory
• Provides an improved turn-around time between
  various tools

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New methodology cont.

• Only data that is modified by one tool needs to
  be addressed by other effected tools
• A circuit designer is able to make changes to the
  block layout plan without involving a different
  person to do the layout design
• Changes in interconnect parasitic values are
  updated in the common data model
• Timing analyzer is able to perform incremental
  analysis of the change

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results
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Results cont.

• In traditional approach, the effort spent in
  circuit and layout design was almost equal
• When layout planning data are available during
  the circuit design stage, the circuit design time
  increases (about 1.25X).
• However, there is a significant decrease in the
  layout design time, which includes the time spent
  in fixing layout (about 1/3X).

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Results cont.

• For a typical datapath block the average time for
  post-layout fixing of critical paths improved
  from over two weeks to less than a week
• This reduces the overall design time by about 25

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Future work

• During circuit design, if a cell cannot be
  synthesized using top-down planning a bottom-up
  correction must be done.
• If several such iterations occur productivity is
  down. New cell synthesis algorithms are needed
• Another area of exploration is to combine layout
  information even earlier in the design cycle,
  namely during logic synthesis

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Summary and conclusuions

• Old design approach vs. new design approach
• By integrating circuit design with layout
  planning, we have improved the overall design
  time.
• Results from a recent microprocessor design
  project support the need for layout planning

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Authors' Biographies

• Bharat Krishna is the layout planner
  project
• leader in the NIKE/DT department.
• He received a M.S. degree in computer engineering
  from Syracuse University in 1994 and a B.Sc.
  degree in electrical engineering from the
  University of Khartoum, Sudan in 1991
• Gil Kleinfeld is the FCDE group leader
  in the
• Nike/DT department. He received a B.Sc.
  
• degree from Tel-Aviv University in
  mathematics and computer science.

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THE END