SYNTHESIS OF APPLICATION SPECIFIC VLIW PROCESSORS

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SYNTHESIS OF APPLICATION SPECIFIC VLIW PROCESSORS

• Under the supervision of
• Prof. Anshul Kumar
• Prof. M. Balakrishnan
• December 3,2001

Varun Raj (98157) Bhuvan Middha (98133)
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Architectural Choices for high performance

• ILP must be exploited for high performance.
• VLIW better than superscalar better possibility
  of customization
• Clustered VLIW architecture for high performance
• Special/Customized FUs which are application
  specific.

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Clustered Architecture
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Why Customized FUs ?

• Chaining a sequence of operations reduces
  computation time.
• Limited Resolution Operation leads to faster
  hardware.
• Concurrent Operations within a group more easily
  parallelized.
• Reduction in Register Pressure.

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OBJECTIVE

• Create a generic model of the proposed VLIW
  architecture.
• Develop a test bed for the proposed VLIW
  architecture.
• Case Studies of mapping applications to the
  proposed VLIW architecture.
• Identification of custom FUs for a given
  application
• Estimating the impact of custom FUs on
  performance.

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TARGET ARCHITECTURE
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Target Architecture (Contd.)

• Core provides default implementation for any part
  of the application
• Core can also be generic in a limited sense.
• Architecture re-adaptation for small changes
  easy.
• Custom FUs mapped to configurable hardware like
  FPGAs.

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Spectrum of Custom FUs

• MISO (Multiple Input Single Output)
• Basic MIMOs (Multiple Input Multiple Output)
• MIMOs with load/store.
• MIMOs with conditionals.
• Loops

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TRIMARAN

• A machine description facility for describing ILP
  architectures.
• A parameterized ILP architecture called HPL-PD
• A compiler front-end called IMPACT, for C
• A compiler back-end called ELCOR
• An extensible IR
• A cycle level simulator of the HPL-PD
  architecture.
• An integrated GUI for configuring and running
  TRIMARAN

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Trimaran Compiler Infrastructure
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Extending Trimaran MISOs

• Prototype declaration of a functionIntended
  Application Modified
  Applicationmain()
  int miso_fun(int a,int b, int c)
  ...
  main()
  ... d (ab) (bc)
  dmiso_fun(a,b,c)
  
  
• External Function Call in Trimaran Bridge Code

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Extending Trimaran MISOs
Sources(a,b,c)
Sources(a,b,c)
Destination(d)
Destination(d)
NEW_OPd a b c
s_time(1)
s_opcode(MNEWOP) flags(sched)
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Defining NEW_OP

• MDESOF_ia(src(FT_i FT_i FT_i) dest(FT_i))OL_newo
  p(time(1))R_newop()RU_newop(use(R_newop)
  time(0))RT_newop(use(RU_newop))SA_newop(format(O
  F_ia) latency(OL_newop) resv(RT_newop))MNEWOP(alt
  (SA_newop))NEW_OP(op(MNEWOP))
• SimulatorNEW_OP ? I , I , I I dest1
  (src1 src2) (src2 src3)

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Extending Trimaran MIMOs

• Void return type for prototype functionIntended
  Application Modified
  Applicationmain()
  void mimo_fun(int a,int b) ...
  
  main()
  ... c(ab)
  int ret_1,ret_2 ...
  
  scanf(d d , ret_1,ret_2)
  d(a-b)
  mimo_fun(a,b) printf(c,d)
  printf(ret_1,ret_2)
  
  

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Extending Trimaran MIMOs

• External function call in Trimaran Bridge Code
• Destinations of NEW_OP set as registers reserved
  for the purposeNEW_OP ret_1 ret_2 a b
  s_time(1) s_opcode(MNEWOP)
• Semantics defined in the simulator as NEW_OP ?
  I , I I , I dest1src1 src2 dest2src1 -
  src2

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Case study FFT

• N floating point data points (N is a power of 2)
• Butterfly Operation
• 2 special functional units each with latency 1

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Butterfly Operation
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FFT results
No of cycles
n
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FFT results
Total no of operations
n
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Proposed Work

• Enhancing the architecture
• Pipelined and multicycle FUs within architectural
  constraints
• Enhancing the framework
• MIMOs with load/store
• Implementation possibilities of loops and
  conditionals within a FU
• Considering a bigger application and mapping it
  to special FUs and evaluate performance gain