2002 VLSI Symposium

1
2002 VLSI Symposium

• Executive Committee Meeting
• 2/5/02

2
Review of 2001 Circuits Symposium
Submitted
Accepted
3
Preview of 2002 Symposium

• Final Paper Selection Meetings upcoming
• 2002 Circuits
• 226 Submissions (193 in 2000)
• 84 Technical sessions
• 2002 Technology
• 231 Submissions (260 in 2000)
• 84 Technical sessions

4
NAE Technical Program Committee

• 25 turnover from the last committee
• Total 22 committee members
• 2 from Canada, 2 from Europe
• 27 from Universities
• TPC expertise

5
Invited papers - Circuits

• 1. On-chip Interconnect - Where is it going?
• Speaker J. Meindl
• Trends in interconnects, past and future,
• high performance and low power
• Impact on SOC, SOP
• 2. Biomedical Implantable Electronics
• Speaker K. Wise (Univ or Michigan)
• Talk will cover history, state of the art, and
  the view as to where it will go in the future.
• 3. Digital Still Camera Technology
• Spekaer H. Tamayama (Fuji Photo Film)
• 4. Ultra-low power LSI design for Future Mobile
  Communications
• Speaker T. Douseki (NTT)

6
Invited papers - Technology
NAE MOSFET scalability limits and new frontier
devices." Dimitri Antoniadis,
MIT JFE MEMS Tech. for optical, medical and
SOC applications M. Esashi, Tohoku
University (not yet confirmed)
7
Rump Sessions - Circuits

• Scaling limit in a power limited environment,
  Architecture vs. Circuit design
• JFE Prof. Tadahiro Kuroda (Keio Univ.)
• NAE Prof. Ken Yang (UCLA)
• Designing high-performance analog in deep
  sub-micron CMOS
• JFE Dr. Tatsuji Matsuura (Hitachi)
• NAE Dr. Katsu Nakamura (Analog Devices)
• Revolution or evolution for memory technology?
• JFE Dr. Changhyun Kim (Samsung)
• NAE Dr. Hugh MaAdams (TI)
• System on a Chip OR System in a Package?
• JFE Circuits T. Sakurai(University of Tokyo)
• NAE Circuits J. Goodman (Lumic Electronics)

8
Rump Sessions - Technology

• 1 - Device Limits- Potential for novel
  devices
• 2 - Next Generation Memory
• 3 - Future Lithography roadmap
• Organizers C. Dennison and T. Eimori
• J - System on a Chip OR System in a Package?
• JFE Circuits T. Sakurai(University of Tokyo)
• NAE Circuits J. Goodman (Lumic Electronics)

9
Short Course - Circuits

• Organizers Dr Stephen Kosonocky (NAE), Dr.
  Koichiro Ishibashi, STARC (JFE)
• Title Leakage Power Reduction Techniques for
  Digital Circuits
• (Tentative topics and speakers)
• 1. Technology overviewHow leakage components
  will scale David Frank (IBM)
• 2. Techniques for variable well bias
  Hitachi?
• 3. Methods for Power Supply decoupling
  Hitachi/Toshiba?
• 4. Leakage sensitive logic families
  Intel?
• 5. TBD
• 6. TBD

10
Short Course - Technology

• Organizers C.S. Pai and H. Ishiuchi-san
• Title Key Technology Challenges for sub-70nm
  VLSI
• (Tentative topics and speakers)
• Advanced Device Technologies H. Iwai
• Novel Device Technologies P. Wong
• Advanced Memory Technology T. Nakamura
• Advanced Interconnect Technologies K. Maex

11
2002 Financials

• Budget assumes 19 decline from 2000 (tracking
  ISSCC)
• Eliminated all expenses possible
• Without impacting conference quality
• Will add items back in if attendance continues to
  improve
• Budget Surplus 8 for both Technology and
  Circuits