Low Density Parity Check Decoder Architecture

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• Low Density Parity Check Decoder Architecture
• Engling Yeo
• yeo_at_eecs.berkeley.edu
• Department of Electrical Engineering and Computer
  SciencesUniversity of California, Berkeley

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Low-density Parity Check Decoder Block
 
Technical Specifications
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Explored Architectures
Check-to-Block (Each Check node connected to 36
Bit nodes)
Bit-to-Check (Each Bit node connected to 4 Check
nodes)

• Fine grained pipelining
• Carrysave Operations
• Shift Registers for Memory and automatic
  pipelining for Address Decoding

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Simulations

• Difficulty with full VHDL simulations for full
  4608 ? 512 matrix.
• Block-level simulations

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Summary

• Power and area dominated by memories.
• More efficient implementation of memories needed,
  e.g. DRAM, slower and smaller flip-flops for
  shift-register implementation.