Architecture and Implementation of LDPC Decoder

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Architecture and Implementation of LDPC Decoder

• Lara Dolecek, Zhengya Zhang
• Professors B. Nikolic, V. Anantharam, and M.
  Wainwright

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Motivation and Project Goals

• Goals
• Propose an efficient architecture for encoding
  and decoding of the LDPC codes, and prove its
  feasibility by implementing it on an FPGA.
• Based on the FPGA implementation, gain insight
  into the behavior of the LDPC codes at very low
  error rates and propose novel constructions void
  of error floors.

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Low Density Parity Check Code
Representation

• Parity Check Matrix
• 
  C1
• 
  C2
• 
  C3
• 
  C4
• V1 V2 V3 V4 V5 V6 V7 V8

• Tanner Graph
• V1
• V2
  C1
• V3
• 
  C2
• V4
• V5
• 
  C3
• V6
• 
  
• V7
  C4
• V8

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Decoding via Message Passing

• bits to checks checks to bits
  bits to checks ..
• 
  
  hard
  decision
  (either all checks satisfied
  or
• initialize
  maxIter reached)

v1
c1
v2
.
v3
c2
c2?v4
v4?c2
.
v4
HD(v4)1if 0 else
c3
v5
.
c4?v4
v4?c4
v6
c4
v7
.
v8
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An Example RS-based LDPC

• Construction
• Shorten a Reed-Solomon code (nq-1,kq-r1) into
  Cb by preserving only the last two information
  symbols.
• Construct Cb(1) as a subcode of Cb containing
  all multiples of a c in Cb whose weight is r.
• Properties
• By construction, there are no cycles of length 4
  and the minimum distance is large.
• Each row of H has weight r.
• Each column of H has weight c.
• No error floors observed.

• 3. Partition the resulting code Cb into cosets of
  Cb(1) Cb(2), , Cb(q).
• 4. For each coset Cb(j), define a matrix Aj whose
  rows are symbol locators of elements in Cb(j).
• 5. The resulting parity check matrix is
• H A1 Act
• Example n 240, m 8, r 15, c 5

I. Djurdjevic, IEEE Comm. Letters, Jul. 2003
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Error Floors

• Flattening of a BER-SNR waterfall curve occurs
  beyond the reach of a simulation.
• Usually due to the so-called near-codewords,
  trapping sets, etc.
• Lack of an analytical tool for describing error
  floors for different channels necessitates the
  FPGA implementation.

Simulation and error floor predictions for
regular (3,6) LDPC codes From top Margulis graph
(n2640), an n2048 code, an n2640 code, and
an8096 code T. Richardson, Allerton 2003
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Check and Bit Node Implementation

• Using log-domain simplification, node
  implementations can be simplified.
• Check node Look up add subtract
  (marginalize) Look up.
• Bit node add subtract (marginalize).
• Good coding performance can be achieved with
  arithmetic precision of 3-5 bits only.
• Lookup table can be implemented in simple
  combinatorial logic.
• Iteration is terminated when a preset threshold
  is reached.

E. Yeo, B. Nikolic, and V. Anantharam, IEEE
Comm. Magazine, Aug. 2003
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Fully Parallel Architectures
Direct-mapped architecture using an interconnect
fabric
Structured architecture that exploits the
regularity of the parity check matrix
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Partially Parallel Architecture
Line up check node (horizontal) and bit node
(vertical) groups
Partition the H matrix into regularly structured
groups
Parallel process among multiple groups and serial
process checks inside the group
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Future Research

• Code construction
• Experiment with existing code constructions and
  investigate the nature of error floors.
• Architectural exploration
• Flexible and efficient architecture which allows
  for fast prototyping of different code
  constructions.
• Error floor simulation
• Real-time hardware emulation of codes to verify
  BER performance.