Programmable Logic

1
Programmable Logic

• Digital Design EE2C2

2
Programmable Logic Syllabus

• This course of lectures deals with the technology
  and programming of programmable logic devices
• The topics that will be covered include
• Technologies fuse, anti-fuse, MOSFET, RAM
• Programmable ROM, EPROM
• Combinational and sequential logic using PROMs
• Programmable array logic (PAL)
• Programming PALs - hardware definition language
• Versatile PALs
• Generic Array Logic (GAL)
• Combinational and sequential logic using
  PALs/GALs
• Field-programmable gate arrays (FPGA)

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Programmable Logic Prerequities

• You should be familiar with the following topics
• SE1EB5 Computer and Internet Technologies
• Boolean algebra
• Karnaugh maps and Boolean simplification
• Logic gates
• Implementation of combinational systems
• Hazards
• Flip-flops
• Implementation of sequential systems
• SE1EC5 Engineering Mathematics
• EE2C2 Digital Design
• Finite-state machines

4
Programmable Logic

• Programmable logic devices (PLDs) are
  increasingly being used instead of standard TTL
  or CMOS gates
• Types of PLD include PROMs, PLAs, PALs, GALs and
  FPGAs
• The logic function of PLDs is determined by the
  state of a number of internal links
• A hardware definition language (HDL) such as VHDL
  is used to specify the function of PLDs
• The HDL is compiled on a computer and downloaded
  to the device by a special-purpose programmer.

5
Programmable Logic

• PROM Programmable read only memory.
• PLA Programmable logic array.
• PAL Programmable array logic.
• GAL Generic array logic.
• FRGA Field programmable gate array.

6
Programmable Logic

• A single PLD can replace a number of standard
  logic gates with the following advantages
• reduced area on circuit board
• higher speed
• lower power consumption
• reduced cost
• increased reliability
• design changes without PCB modification
• Typically re-programmable devices are used during
  the development phase
• One-time-programmable devices are used during
  production

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Programmable AND
8
Programmable OR
Uses the same design as the previous slide,
however the diode is connected differently
9
Programmable Logic

• Devices are programmed by making, or breaking,
  connections within the device.
• There are 6 main technologies
• Mask programmed
• Fuse
• Anti-fuse
• Floating-gate UV erasable
• Floating-gate electrically erasable
• RAM-based

10
Mask Programmed Logic

• Mask-programming must be performed by the
  manufacturer
• The process is identical for all devices except
  for the final metallisation
• The final metallisation is controlled by a mask
  specified by the user
• Turn-round time is long
• Cost of mask is very high making this method
  only suitable for very large number of identical
  devices
• Mask-programmed logic is non-volatile and
  radiation-hard

11
Fuse Programmed Logic

• Fuse logic is one-time-programmable
• Fuse is a two-terminal device that is normally a
  low resistive element and may be blown resulting
  in an open circuit
• Typical materials are nichrome and polysilicon
• There may be reliability problems - the
  evaporated fuse material settles elsewhere on the
  surface of the device
• Fuse element is non-volatile and radiation-hard

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Anti-Fuse Programmed Logic

• Anti-fuse logic is one-time-programmable
• Anti-fuse is a two-terminal device that is
  normally an open circuit and may be programmed to
  a low resistance
• This is done by destructively breaking down an
  insulating layer
• Typical programmed resistances range from 25 to
  500 O
• Anti-fuse is non-volatile and radiation-tolerant
  certain versions can be made radiation-hard.

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Metal-Metal Anti-Fuse

• Metal layers (tungsten, titanium) are separated
  by SiO2 insulator and amorphous silicon

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Floating-Gate MOSFET UV Erasable

• Floating-gate MOSFET devices which can be
  reprogrammed
• UV erasable, electrically programmable
• Data retention gt 20 years at 125 C
• Ceramic package incorporates a quartz window (to
  allow uv exposure) which is expensive
• Not radiation-hard

15
Floating-Gate MOSFET

• Erase using short-wavelength ultra-violet light
  photoelectric emission gives floating gate a ve
  charge
• Program by breaking down the drain-substrate
  diode hot electrons cross insulator giving
  floating gate a -ve charge

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Floating-Gate MOSFET

• Erased gate has positive charge which lowers
  threshold voltage
• Transistor operates normally
• Programmed gate has negative charge which
  raises threshold voltage
• Transistor is always OFF

17
Floating-Gate MOSFET Electrically Erasable

• Floating-gate MOSFET devices which can be
  reprogrammed
• Electrically erasable, electrically programmable
• Data retention gt 20 years at 125 C
• Inexpensive plastic packaging
• Not radiation-hard

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Floating-Gate MOSFET Electrically Erasable

• Erase is by Fowler-Nordheim tunnelling which
  establishes a positive charge on the floating
  gate
• Program by breaking down the drain-substrate
  diode hot electrons cross insulator giving
  floating gate a -ve charge

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RAM-Based PLDs

• A flip-flop stores the state of each link
• RAM-based PLDs are re-programmable and volatile
• RAM-based PLDs allow fast in-circuit
  reconfiguration
• The link map must be downloaded from an external
  source on power-up
• Several transistors per link leads to large chip
  size
• RAM-based PLDs are radiation-hard, but device
  storing the link map may be radiation-sensitive

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RAM-Based PLDs

• Each link consists of a flip-flop together with a
  transistor switch

Vcc
Flip-flop
Link
21
Programmable ROM

• The most familiar programmable logic device is
  the programmable read-only memory (PROM, EPROM,
  EEPROM or FlashRAM)
• PROM typically has 10 to 19 inputs (address
  lines) and 8 outputs (data lines)
• n address lines specify 2n locations each
  location contains an 8-bit data word
• Each of the 8 outputs is therefore a completely
  general combinational function of the inputs

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Programmable ROM
Fuses are represented by the X symbols and can be
broken or left to determine OR gates as part of
the logic matrix. This defines the outputs W, X,
Y and Z.
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EPROM ST M27C1001
EPROMs can make dynamic or stable hazards. Since
the device does not accept all data at the same
time, spurious data can be seen between the logic
pluses
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EPROM ST M27C1001
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Combinational Logic Using PROMs
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Combinational Logic Using PROMs
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Combinational Logic Using PROMs
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Combinational Logic Using PROMs

• Data to be programmed into a PROM is normally
  specified in data file which is uploaded to a
  PROM programmer
• A common format for specifying PROM data is
  Motorola Srecords
• Unfortunately software is not available for
  automatically generating PROM data files from
  logic functions
• In most cases the data must be entered manually
  into the PROM programmer
• This can be time-consuming and error-prone

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Combinational Logic Using PROMs

• The process of defining the PROM data can be
  automated by writing a computer program
• Example the 8-bit square root of a 16-bit
  integer number
• include ltiostream.hgt
• include ltmath.hgt
• const unsigned int address_lines 16
• const unsigned int rom_size 1 ltlt address_lines
• unsigned int data(unsigned int address)
• return (unsigned int) sqrt((double) address)

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Combinational Logic Using PROMs

• Function dump_rom() will call data() with all
  possible address values, and print out the
  result
• void dump_rom()
• unsigned int a
• cout.setf(ioshex)
• cout.fill('0')
• for (a 0 a lt rom_size a)
• cout ltlt "rom"
• cout.width(4)
• cout ltlt a ltlt " "
• cout.width(2)
• cout ltlt data(a) ltlt "\n"

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Combinational Logic Using PROMs

• In practice the program would need to be modified
  to output the data in S-record (or similar) form

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Combinational Logic Using PROMs
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Sequential Logic Using PROMs

• Sequential logic systems are usually formalised
  as finite state machines (FSMs)
• The elements of synchronous FSMs are
• A state memory consisting of D-type flip-flops
• Combinational logic to generate the next state
  variables from the present state variables and
  the inputs
• Combinational logic to generate the outputs from
  the present state variables and the inputs
• The combinational logic can be implemented using
  PROMs

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Sequential Logic Using PROMs
The clock frequency must be set appropriately
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Sequential Logic Using PROMs
Sequence detector

• A string of 0s and 1s is assumed to be applied to
  the input X synchronously with the clock
• The output Z should become 1 for a single clock
  period if the sequence 1001 appears on the input

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Sequential Logic Using PROMs
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Sequential Logic Using PROMs
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Sequential Logic Using PROMs
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Sequential Logic Using PROMs
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Sequential Logic Using PROMs

• There are some drawbacks to PROM-based FSMs
• The clock frequency is limited by the response
  time of the PROM
• Following a clock transition the outputs will
  exhibit static and dynamic hazards
• PROMs are larger, more expensive and power hungry
  than alternative PLDs
• Software is not available for programming
  PROM-based FSMs

41
Programmable Array Logic

• Programmable Array Logic devices (PALs) typically
  generate 8 output logic functions of 10 inputs
  and 6 of the outputs themselves
• The logic functions are not completely general as
  in PROMs but typically allow 8 product terms
• The feedback means that PALs can be programmed to
  act as asynchronous FSMs
• Some PALs contain D-type flip-flops on their
  outputs and so can be used as synchronous
  counters and FSMs

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Programmable Array Logic

• Any realistic logic system can be implemented on
  a PAL.
• A product term is defined as any term that
  defines the logical function. For example, the
  product terms of (1) are (2).
• F A BCD (1)
• A and BCD (2)
• Any simplification of logic coding can be
  performed in software since for any realistic
  system there would be too many operations to
  simplify by hand.
• Furthermore reading of the fuse map can be denied
  by the setting of a fuse bit. This should secure
  the work that went into the design of the device
  and stops reverse engineering for sequential
  systems but not for combinational ones.

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Programmable Array Logic
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Programmable Array Logic MMI PAL16L8

• Technology bipolar, one-time programmable
• Outputs 8, inputs 10, feedback 6
• Number of product terms 7
• Package 20-pin DIL or surface mount
• Delay time input change to output 25 ns
• Power supply 120 mA at 5 V
• Cost N/A (replaced by V series PALs and GALs)

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Programmable Logic PAL16L8

• A completed circuit diagram is shown.
• It can be seen that there are 16 inputs to the
  system which equates to 8 outputs and that there
  are 6 feedback lines included in the 16 input
  lines.

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Programmable Logic PAL16L8
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Combinational Logic Using PALs

• The logic function of a PAL is defined by
  making/breaking appropriate links in the AND
  matrix
• The link data could in principle be entered into
  the PAL programmer manually
• In practice the logic function is specified
  either by schematic entry or by hardware
  description language (HDL)
• The most popular HDLs for small programmable
  logic devices are ABEL, CUPL, OPAL and PALASM
• No variant of HDLs are inter-compatible

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Combinational Logic Using PALs

• The specification written in a HDL is compiled on
  a PC to produce a JEDEC fuse map file
• Most HDL compilers incorporate a simulator which
  allows the design to be tested before programming
  a device
• The JEDEC file is uploaded to the PAL programmer
• This device is then programmed
• A security link on the device can be set to
  prevent the link data from being read (to prevent
  reverse engineering)

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Combinational Logic Using PALs
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CUPL Definition File Boolean Expression
Students will not be expected to be able to
perform PAL programming under exam conditions
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CUPL Documentation File
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CUPL Documentation File
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JEDEC Output File
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PAL16L8 Implementation
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CUPL Definition File Truth Table
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CUPL Documentation File
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CUPL Simulation
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CUPL Simulation
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CUPL Definition File From Schematic
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CUPL Definition File From Schematic
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CUPL Definition File From Schematic
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CUPL Definition File From Schematic
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CUPL Definition File From Schematic
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Registered PALs PAL16R8
The devices has 16 inputs and 8 outputs It is
also important to note that these outputs are
attached to D-type flip-flops as indicated by the
R This device is now obsolete
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Registered PALs PAL16R8
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Versatile PALs

• Versatile PALs have a macrocell on each output
• Each macrocell can be programmed to be
  combinational or registered, and active-low or
  active-high
• The macrocell on each output allows a versatile
  PAL to emulate a range of simple PALs
• For example a PAL16V8 can replace any 20-pin PAL
  such as PAL16L8, PAL18R8, PAL16R4, PAL16R6,
  PAL16H8
• Consequently simple PALs are now effectively
  obsolete
• It is important that students fully understand
  VPALs

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Versatile PALs PAL16V8
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Versatile PALs PAL16V8
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Versatile PALs PAL16V8
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Versatile PALs PAL16V8
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Versatile PALs PAL16V8
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Generic Array Logic

• GALs are similar to versatile PALs except that
  they use floating-gate/electrical erase
  technology
• GALs can therefore be reprogrammed
• GALs use CMOS technology resulting in a lower
  power consumption than bipolar technology PALs
• GALs are as fast, or faster, than bipolar
  technology PALs
• Being reprogrammable GALs can be fully tested by
  the manufacturer
• This device is not radiation hard

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Generic Array Logic Lattice GAL16V8

• Technology cmos, re-programmable
• Outputs 8, inputs 10, feedback 6
• Number of product terms 8
• Package 20-pin DIL or surface mount
• Delay time input change to output 3.5 ns
• Power supply 75 mA at 5 V
• Cost 2
• This is an example of a very fast device, but is
  not the fastest

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Sequential Logic Using PALs
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Sequential Logic Using PALs
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Sequential Logic Using PALs
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Sequential Logic Using PALs
This shows a Johnston-code counter when not
started in recognised state.
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Sequential Logic Using PALs
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Sequential Logic Using PALs
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Finite State Machines Using PALs
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FSM (Moore) Definition File
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FSM (Moore) Definition File
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FSM (Moore) Documentation
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FSM (Moore) Simulation
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FSM (Moore) Simulation
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FSM (Mealy) State Diagram
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FSM (Mealy) State Definition File
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FSM (Mealy) Documentation
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FSM (Mealy) Simulation
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FSM (Mealy) Simulation
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Bus Systems

• A common requirement in digital electronics is to
  connect a number of devices to a common data path
• This arrangement is used in microprocessor
  systems
• Such a common data path is called a bus
• A bus consists of a number of wires, each wire
  carrying one bit of a complete word
• Bus systems will not be examined

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Bus Systems
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Tri-State Logic

• This is also sometimes called "three-state logic
• Tri-state logic devices have three possible
  output states
• logic 0
• logic 1
• undefined (high impedance) X
• Such devices have, in addition to the normal
  inputs, a tri-state control input
• This is usually called "output enable or OE

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Tri-State Logic
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Tri-State Logic

• The outputs of tri-state devices can be connected
  together
• One, and only one, device connected to the bus
  can have OE1, all other devices must have OE0
• A combinational logic circuit should prevent more
  than one device having OE1
• Each of the outputs on a GAL has tri-state
  capability
• The tri-state control is a logic function of the
  inputs, but is limited to one product term

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Open-Collector Logic
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Open-Collector Logic
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Open-Collector Logic

• Some bus systems employing open-collector logic
  use an active-low representation
• When active-low logic is used the connection of
  open-collector gates gives "wired-OR
• The speed at which open-collector bus systems can
  operate is determined by the bus capacitance and
  the value of the pull-up resistor
• If the total bus capacitance is 200 pF and the
  pull-up resistor is 500 O then the time constant
  is 100 ns

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Open-Collector Logic
100
Address Decoding using GALs
101
Address Decoding using GALs
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Address Decoding using GALs
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Address Decoding using GALs
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Address Decoding using GALs
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Asynchronous FSM using PALs

• Pulse gate state diagram
• Pulses on input p are gated by q

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Asynchronous FSM using PALs
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Asynchronous FSM using PALs
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Asynchronous FSM using PALs
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Asynchronous FSM using PALs
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Asynchronous FSM using PALs
111
Complex PLDs and FPGAs

• The devices discussed so far (PALs and GALs) are
  simple PLDs (SPLDs)
• These are suitable for implementing simple
  combinational and sequential logic functions
• For more complex functions it is necessary to
  use
• Programmable Logic Arrays (PLAs), or
• Field-Programmable Gate ARRAYs (FPGAs)

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Programmable Logic Array
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Field-Programmable Gate Array
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Field-Programmable Gate Array
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Field-Programmable Gate Array

• Typical FPGA QuickLogic pASIC3
• Technology CMOS 4-layer metal
• Programming Antifuse
• Usable logic gates 4000 ? 60000
• Logic cells 96 ? 1584
• Flip-flops (max) 218 ? 2692
• I/O (max) 74 ? 316
• Cell speed 2 ns
• Routability 100
• Operating voltage 3.3 V (5 V tolerant)
• Packages PLCC, TQFP, PQFP, PBGA

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pASIC3 Logic Cell
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pASIC3 Logic Cell

• A pASIC3 logic cell can be configured to be
• one 16-input AND gate
• two 6-input AND gates two 4-input AND gates
• two 6-input AND gates two 21 multiplexers
• two 6-input AND gates one 41 multiplexer
• one 5-input XOR gate
• one 3-input XOR gate one 2-input XOR gate
• one D-type flip-flop with async preset and clear
• one RS-type flip-flop with async preset and clear
• one JK-type flip-flop with async preset and clear
• one T-type flip-flop with async preset and clear
• etc ...

118
FPGA Development Tools

• There are two approaches to FPGA design
• Schematic entry
• The design is entered as a hierarchical schematic
  using gates and flip-flops
• This is typically used for small to medium size
  systems
• Schematics are easy to understand and modify
• HDL entry
• The design is specified using a HDL (VHDL or
  Verilog)
• Large systems are almost always specified using a
  HDL
• Difficult to get an overview of a design
  specified using a HDL

119
Hardware Definition Languages

• VHDL
• Very High speed integrated circuit Description
  Language
• Initiated by American DoD as a specification
  language
• Standardised by IEEE
• Verilog
• First real commercial HDL language
• Industry standard for many years
• Standardised by IEEE

120
Functional Simulation

• Functional simulation can be done after the
  schematic has been entered or a HDL file has been
  created
• Functional simulation gives information about the
  logical operation of the system
• It does not provide any information about timing
  delays
• The functional simulation uses a stimulus file
  which defines the input signals to predict the
  outputs
• The simulation examples given for the PAL/GAL
  designs are functional simulations

121
Place and Route

• If the results of functional simulation are
  satisfactory then the design is compiled to
  produce an EDIF netlist
• EDIF files can be exchanged between different
  design tools
• A place and route tool is used to fit the design
  to a specific FPGA device
• This process can be very time-consuming,
  particularly if the device usage approaches 100
• The result is a fuse map file that can be used to
  program the FPGA

122
Post-Layout Simulation

• Once the place and route operation is complete
  the circuit delays can be back-annotated to the
  netlist
• These delays are estimated from the track
  resistance and parasitic capacitance
• This allows a timing simulation to be performed
  which incorporates realistic delays
• It is at this stage that hazards and races may
  become apparent (that would not appear in the
  functional simulation)
• If the post-layout simulation is satisfactory
  then the device can be programmed