MI1

1
Memories I

• Dr. T.Y. Chang
• NTHU EE
• 2007.11.20_22_27

2
Contents

• Introduction
• SRAM
• DRAM
• Mask ROM
• Sedra/Smith V.5 Chapter 11

3
Memory Types

• Main Memories
• Fast
• Random Access
• High-performance
• Mass Storage Memories
• Mass storage
• Low-cost

4
Memories Classifications (Neamen)

• Random Access Memories (RAMs)
• Volatile lose data when power off
• Search
• Content-Addressable Memories (CAMs)
• Store data
• Static RAM (SRAM)
• Faster, 6 Trs/cell
• Dynamic RAM (DRAM)
• High Density, 1 Tr and 1C per cell, need refresh

5
Memories Classifications

• Read-Only Memories (ROMs)
• Nonvolatile retain data even power off
• Store OS, fixed data
• Field Programmable Memories
• Nonvolatile
• EPROM, EEPROM, FPGA, Flash, FRAM

6
Memory Architecture (Neamen)

• Inputs Address lines, Data line(s), R/W control,
  Enable (Optional)
• Output data line(s)

7
RAM Architecture

• Decoder
• N address lines decode to 2N lines
• Only one selected
• Memory array
• Control circuit

8
11.4.1 SRAM Cell

• Bit and
• Word line
• Two inverters and two switches

9
SRAM Read Operation

• B and precharge to VDD/2 (or VDD)
• Assume V 0 and VQ VDD
• Switches on
• Ex 11.2

10
SRAM Write Operation

• B and charge to 0 and VDD, respectively.
• Assume V 0 and VQ VDD
• Switches on

11
DRAM

• Dynamic RAM
• One switch, one data line, and a Cap
• Fresh required (refresh)

12
SRAM Sense Amplifier

• Usually, 1 SA/col.
• SA off if Fs0
• Before Read opr, FP1 ? B VDD/2
• then FP0, WL1
• then Fs1

13
SRAM SA Functions

• In R1, the sense amplifier causes the initial
  small increment DV(1) to grow exponentially to
  VDD.
• In R0, the negative DV(0) grows to 0.
• Complementary signal waveforms develop on the B
  and lines.

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Ex. 11.3 in p 1041

• Given (W/L) ratios and other information to find
  rise/fall time in SRAM cell.

15
DRAM SA

• Dummy cell required

16
Row-Address Decoder

• Only one row is selected

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Column-Address Decoder I

• Two types
• Pass-Transistor Multiplexer

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Column-Address Decoder II

• Tree decoder

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Read Only Memory

• MOS ROM
• Mask Programmable ROM
• Final step(s) for connections in Fabrication
• Programmable ROM
• PROM
• EPROM
• EEPROM

20
MOS ROM

• 8 words x 4 bits (32 bits)

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Problems (Not HW)

• For a 1Mx1 RAM, how many address lines are
  required?

22
Decoder (Neamen)
(a4a3a2a1a0) a4a3a2a1a0 (00110)
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SRAM Cells NMOS (Neamen)
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CMOS SRAM Cell with pull-up
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Read Operation

• IMNA(S)ltIMN1(T) (IMNB(S)ltIMN2(NS))
• KnA(VDD?Q?VTN)2ltKN12( VDD ?VTN )Q ?Q2 QVTN
• (W/L)nA/(W/L)n1lt 2(VDD VTN) ?3V2TN /(VDD ?2VTN
  )2
• VDD 3, VTN 0.5
• (W/L)nA/(W/L)n1lt0.56

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Write Operation

• IMp2(S)ltIMNB(T) (IMP1(S)ltIMNA(T))
• Kp2(VDDVTP)2ltKNB2( VDD ?VTN )Q ?Q2 QVTN
• (W/L)p2/(W/L)nBlt (kn/kp)2(VDDVTN)?3V2TN /(VDD
  VTp )2
• VDD 3, VTN 0.5, VTP ? 0.5, then
  (W/L)p2/(W/L)nBlt0.72

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SRAM R/W Circuitry
Vo
28
Write
29
DRAM Cell

• Logic-0 0 V
• Logic-1 VDD ? VTN

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DRAM Operations

• Dummy Cell CR0.5 CS
• Init VCR0, ?21 Precharge, CEbar1
• Read ?20, CEbar0, charge redistrib.
  D-WLRowSel WL1
• R0 V1ltV2
• R1 V1gtV2

31
ROM

• Mask ROM
• Select Y
• Select X
• Q ? Vo0
• No Q ? Vo1

0110 1000 0101 1010
32
PROM (Neamen)

• Large current
• to blow out fuse
• to connect by anti-fuse

• Blow fuses by user
• Select X
• Select Y
• Vo 0 fuse exits
• Vo 1 No fuse

33
EPROM
34
EPROM

• Floating gate

35
EPROM I-V Characteristics

• Floating gate

36
EPROM During Programming
37
EPROM Program and Erase
Ref. Book D.A. Hodges, H. G. Jackson, R. A.
Saleh, "Analysis and Design of Digital
Integrated Circuits," 3rd Ed., McGraw Hill,
2004. Chapter 9.
38
EEPROM