Playstation2 Architecture

1
Playstation2 Architecture

• Architecture
• Hardware Design

2
System Overview

• The listing below is a clean view of the design
  behind the Playstation2 hardware

3
CORE CPU

• General Purpose MIPS variant
• 128bit SIMD integer multimedia extensions
• ICACHE and DCACHE
• Scratch Pad RAM
• Dedicated FPU coprocessor

FPU
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Dedicated FPU

• FPU Floating-Point Processing Unit
• This unit is used to handle fast floating-point
  operations
• Playstation2 is optimized for 32bit operations.
• double data type or 64bit floating operations
  are much slower and cause major bottle necks

5
SIMD

• SIMD - Single Instruction Multiple Data
• 128bit SIMD allows for a single operation to be
  applied to four integers / floats
• The operations that can be performed are specific
  to the CPU
• SIMD is especially useful in games for all of
  its complex vector and matrix math

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How SIMD Works

• If given two packed data elements the operation
  is performed to all of the components in each
  element

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Typical System LayoutCache Dependency

• The cache is found on the CPU and has faster
  access times than system memory

8
CACHE

• The purpose of cache is to reduce the time it
  takes to execute redundant operations or access
  data values
• ICACHE Instruction Cache
• DCACHE Data Caches
• SPR Scratch Pad RAM

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How Cache Works
Priority Cache System Memory
10
Hardware Controllers

• A controller is a device used to interface and
  communicate with a piece of hardware
• Every major component has a controller for their
  interface
• The user application will typically use registers
  or interrupt calls to access the controller
  devices

11
DMA Controller

• DMA Direct Memory Access
• DMAC is the arbiter for the main bus
• Used to transfer data between processes
• Allows for some parallelism

12
Vector Units

• Playstation2 has two vector units that are
  similar but not the same
• VU0 is the CPUs alternate processing unit.
• VU1 is the GSs alternate processing unit
• Each Unit has a direct pipeline to its alternate
  processor
• Vector Units are designed for vectors
• (imagine that)

13
DMAC and Graphics

• DMAC feeds VU1 with needed data, and does so with
  no CPU intervention
• Data that is transferred to VU1 is resident on
  system RAM
• CPU is now free to process any instructions that
  have made hits in the instruction cache
• CPU can also access any information in the data
  cache

14
VU Architecture

• VU0/1 each have access to 32 float registers and
  16 integer register
• Float registers are not your average PC style
  registers they are 128bits in size
• 128bits can conveniently fit 4 float values at
  once (very similar to SIMD architecture)
• Integer registers are typically used as loop
  counters and address calculators

15
VU0

• VU0 has two bus lines
• One bus is dedicated to the CPU
• The other bus is used to communicate with all
  other devices
• Access to shared bus lines always need to be
  monitored
• VU0 has 4KB of

dedicated
CPU CORE
shared bus
SYS RAM
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Shared Buses and VU0

• Why do we need to monitor shared buses?
• Only one process can access shared devices at a
  time
• Any access operations through a shared bus will
  cause all other processes to wait
• Using the VU registers and reducing RAM access
  will help prevent shared access

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VU1

• VU1 has two bus lines
• Main bus is dedicated to the GS
• Has almost identical functionality as VU0
• Main purpose of VU1 is to process the data before
  the GS
• VU1 has 16KB of

dedicated
GS CORE
shared bus
SYS RAM
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Review

• Playstation2 is like having 4x300 MHz processors
• CPU VU0 VU1 GS
• Cache utilization is the key to reaching the
  limits of this system
• VU0 is primarily for CPU vector operations
• VU1 is dedicated to geometry processing
• GS manages hardware support of triangle
  rasterization