Registers Lab 5

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RegistersLab 5

• Mano and Kime
• Sections 5-2, 5-3, 5-7

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4-Bit Register
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A Generic Register
library IEEE use IEEE.std_logic_1164.all   entit
y reg is generic(width positive) port
( d in STD_LOGIC_VECTOR (width-1 downto
0) load in STD_LOGIC clr in
STD_LOGIC clk in STD_LOGIC q
out STD_LOGIC_VECTOR (width-1 downto 0)
) end reg
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architecture reg_arch of reg is begin
process(clk, clr) begin if clr '1' then
for i in width-1 downto 0 loop q(i)
lt '0' end loop elsif (clk'event and
clk '1') then if load '1' then
q lt d end if end if end process
end reg_arch
Infers a flip-flop for all outputs (q)
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debounce entity
entity debounce is port ( inp, clk, clr in
std_logic outp out std_logic ) end debounce
clk
clr
debounce
inp
outp
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debounce
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debounce architecture
architecture rtl of debounce is signal delay1,
delay2, delay3 std_logic begin process(clk,
clr) begin if clr '1' then
delay1 lt '0' delay2 lt '0' delay3 lt
'0' elsif clk'event and clk'1' then
delay1 lt inp delay2 lt delay1 delay3
lt delay2 end if end process outp lt
delay1 and delay2 and (not delay3) end rtl
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Lab 5 A Single-Cycle Processor
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Add
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Add
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clk_pulse.vhd
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Pcount.vhd
-- A 4-bit up-counter library IEEE use
IEEE.std_logic_1164.all use IEEE.std_logic_unsign
ed.all   entity Pcount is port (
clr in STD_LOGIC clk in STD_LOGIC
q out STD_LOGIC_VECTOR (3 downto 0)
) end Pcount
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Pcount.vhd (cont.)
architecture Pcount_arch of Pcount is signal
COUNT STD_LOGIC_VECTOR (3 downto 0) begin
process (clk, clr) begin if clr '1' then
COUNT lt "0000" elsif clk'event and
clk'1' then COUNT lt COUNT 1 end
if q lt COUNT end process end
Pcount_arch
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dig7seg.vhd
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Prom
Single-cycle microcoded instructions
Additional Instructions
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Prom.vhd
library IEEE use IEEE.std_logic_1164.all use
IEEE.std_logic_unsigned.all   entity Prom is
port ( addr in STD_LOGIC_VECTOR (3
downto 0) M out STD_LOGIC_VECTOR (8
downto 0) ) end Prom  
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Prom.vhd
  architecture Prom_arch of Prom is constant dup
STD_LOGIC_VECTOR (9 downto 0)
"1000010000" constant swap STD_LOGIC_VECTOR
(9 downto 0) "1100010000" constant Sfetch
STD_LOGIC_VECTOR (9 downto 0)
"1110010000" constant plus STD_LOGIC_VECTOR
(9 downto 0) "0101010000" constant oneplus
STD_LOGIC_VECTOR (9 downto 0)
"0101010010" constant invert STD_LOGIC_VECTOR
(9 downto 0) "0101010100" constant orr
STD_LOGIC_VECTOR (9 downto 0)
"0101010110" constant twotimes
STD_LOGIC_VECTOR (9 downto 0)
"0101011000" constant lshift STD_LOGIC_VECTOR
(9 downto 0) "0101011100"
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Lab 5 A Single-Cycle Processor
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Lab5.whp
HEX S_at_ \ 0069 S_at_ \ 0069 0008 lshift \
6900 S_at_ \ 6900 0037 or \ 6937 2 \
D26E S_at_ \ D26E 00A4 \ D312 invert \
2CED 1 \ 2CEE
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Prom.vhd (cont.)
subtype rom_word is std_logic_vector(9 downto
0) type rom_array is array (NATURAL range ltgt) of
rom_word) constant rom rom_array ( Sfetch,
-- then set switches to 08 hex Sfetch,
lshift, Sfetch, orr, twotimes, Sfetch,
plus, invert, oneplus, X0000,
X0000 ) begin process(addr) variable j
integer begin j conv_integer(addr)
M lt rom(j) end process end Prom_arch