Verilog HDL in Low Level Design

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Verilog HDL in Low Level Design

• From Logic gate level
• To Transistor level design

By Theerayod Wiangtong Electronic Department,
Mahanakorn University of Technology
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Outline

• MOS revisit
• Static CMOS combinational circuit
• ASIC (Layout) design tools

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MOS Structure
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MOS Review

• Transistor gate, source, drain all have
  capacitance
• I C (DV/Dt) -gt Dt (C/I) DV
• Capacitance and current determine speed
• MOS symbol

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MOS Capacitor

• Gate and body form MOS capacitor
• Operating modes
• Accumulation
• Depletion
• Inversion

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Terminal Voltages

• Mode of operation depends on Vg, Vd, Vs
• Vgs Vg Vs
• Vgd Vg Vd
• Vds Vd Vs Vgs - Vgd
• Source and drain are symmetric diffusion
  terminals
• By convention, source is terminal at lower
  voltage
• Hence Vds ? 0
• nMOS body is grounded. First assume source is 0
  too.
• Three regions of operation
• Cutoff
• Linear
• Saturation

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nMOS Cutoff

• No channel
• Ids 0

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nMOS Linear

• Channel forms
• Current flows from d to s
• e- from s to d
• Ids increases with Vds
• Similar to linear resistor

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nMOS Saturation

• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source

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nMOS I-V Summary

• Shockley 1st order transistor models

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Example

• We will be using a 0.6 mm process for your
  project
• From AMI Semiconductor
• tox 100 Å
• m 350 cm2/Vs
• Vt 0.7 V
• Plot Ids vs. Vds
• Vgs 0, 1, 2, 3, 4, 5
• Use W/L 4/2 l

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pMOS I-V

• All dopings and voltages are inverted for pMOS
• Mobility mp is determined by holes
• Typically 2-3x lower than that of electrons mn
• 120 cm2/Vs in AMI 0.6 mm process
• Thus pMOS must be wider to provide same current
• In this class, assume mn / mp 2

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Current-Voltage RelationsLong-Channel Device
Second Order Effect
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ID versus VDS
Long Channel
Short Channel
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CMOS Inverter
N Well
PMOS
2l
Contacts
Out
In
Metal 1
Polysilicon
NMOS
GND
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Two Inverters
Share power and ground Abut cells
Connect in Metal
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CMOS Inverter as Switch
V
V
DD
DD
R
p
V
V
out
out
C
C
L
L
R
n
V
V
V
0
5
5
in
DD
in
(a) Low-to-high
(b) High-to-low
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DC Response

• DC Response Vout vs. Vin for a gate
• Ex Inverter
• When Vin 0 -gt Vout VDD
• When Vin VDD -gt Vout 0
• In between, Vout depends on
• transistor size and current
• By KCL, must settle such that
• Idsn Idsp
• We could solve equations
• But graphical solution gives more insight

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Transistor Operation

• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?

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DC Transfer Curve

• Transcribe points onto Vin vs. Vout plot

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Operating Regions

• Revisit transistor operating regions

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Beta Ratio

• If bp / bn ? 1, switching point will move from
  VDD/2
• Called skewed gate
• Other gates collapse into equivalent inverter

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Noise Margins

• How much noise can a gate input see before it
  does not recognize the input?

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Logic Levels

• To maximize noise margins, select logic levels at

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Logic Levels

• To maximize noise margins, select logic levels at
  
• unity gain point of DC transfer characteristic

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Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise time
• From output crossing 0.2 VDD to 0.8 VDD
• tf fall time
• From output crossing 0.8 VDD to 0.2 VDD
• tcdr rising contamination delay
• From input to rising output crossing VDD/2
• tcdf falling contamination delay
• From input to falling output crossing VDD/2
• tcd average contamination delay
• tpd (tcdr tcdf)/2

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Delay Definitions
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Delay Definitions
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Delay Definitions
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Simulated Inverter Delay

• Solving differential equations by hand is too
  hard
• SPICE simulator solves the equations numerically
• Uses more accurate I-V models too!
• But simulations take time to write

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Outline

• MOS revisit
• Static CMOS combinational circuit
• ASIC (Layout) design tools

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Static CMOS Circuit
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Static Complementary CMOS
VDD
In1
PMOS only
In2
PUN

InN
F(In1,In2,InN)
In1
In2
PDN

NMOS only
InN
PUN and PDN are dual logic networks
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
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PMOS Transistors in Series/Parallel Connection
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Threshold Drops
VDD
VDD
PUN
S
D
VDD
D
S
0 ? VDD
0 ? VDD - VTn
VGS
VDD ? 0
PDN
VDD ? VTp
VGS
S
D
VDD
S
D
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Complementary CMOS Logic Style
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Example Gate NAND
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Example Gate NOR
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Complex CMOS Gate
OUT D A (B C)
A
D
B
C
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Standard Cells
N Well
Cell height 12 metal tracks Metal track is
approx. 3? 3? Pitch repetitive distance
between objects Cell height is 12 pitch
2?
Out
In
Rails 10?
GND
Cell boundary
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Standard Cells
2-input NAND gate
A
B
Out
GND
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Stick Diagrams
Contains no dimensions Represents relative
positions of transistors
Inverter
NAND2
Out
Out
In
A
B
GND
GND
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Two Stick Layouts of !(C (A B))
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Connection label layout
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VDD, VSS and Output Labels
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Interconnected
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CMOS Properties

• Full rail-to-rail swing high noise margins
• Logic levels not dependent upon the relative
  device sizes ratioless
• Always a path to Vdd or Gnd in steady state low
  output impedance
• Extremely high input resistance nearly zero
  steady-state input current
• No direct path steady state between power and
  ground no static power dissipation
• Propagation delay function of load capacitance
  and resistance of transistors

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Switch Delay Model
Req
A
A
NOR2
INV
NAND2
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Input Pattern Effects on Delay

• Delay is dependent on the pattern of inputs
• Low to high transition
• both inputs go low
• delay is 0.69 Rp/2 CL
• one input goes low
• delay is 0.69 Rp CL
• High to low transition
• both inputs go high
• delay is 0.69 2Rn CL

Rn
B
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Outline

• MOS revisit
• Static CMOS combinational circuit
• ASIC (Layout) design tools

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Layout

• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor
  size (and hence speed, cost, and power)
• Feature size improves 30 every 3 years or so
• Normalize for feature size when describing design
  rules

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Transistor Layout
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CMOS Process Layers
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Intra-Layer Design Rules
4
Metal2
3
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CMOS Inverter Layout
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Detailed Mask Views

• Six masks
• n-well
• Polysilicon
• n diffusion
• p diffusion
• Contact
• Metal

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Traditional Design tools
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New Design tools
HDL (Verilog)
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Cadence Design Tools Example
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QUESTIONS?
THANK YOU