VHDL Overview

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VHDL Overview
A Quick Start Tutorial
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What does VHDL stand for ?

• VHSIC Hardware Description Language
• VHSIC Very High Speed Integrated Circuits

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HDLs

• VHDLUSA Department of DefenseIEEE Std 1076-1993
• VerilogIEEE Std 1364-1995
• Super Verilog
• SystemC

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HDL applications

• High Level Modeling (Behavioral style)
• Design Entry (Structural RTL styles)
• Simulation (Behavioral style)
• validation by mean of a test bench

dut_tb.vhd
dut.vhd
instantiate design to test
generate stimuli
observe responses
TESTBENCH
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HDL vs. Schematic Entry

• The Design Description is independent from the IC
  Vendors Cell Libraries (in other words
  independent from physical implementation)
• Enable portability
• Foster reuse
• Higher Level of Abstraction (hiding details)
• The design task become simpler
• The design is less error prone
• Productivity is increased

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HDLs vs. Software Languages

• Concurrent (parallel) Statements
  vs. Sequential Statements

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HDL coding Styles

• Register Transfer Level
• Structural
• Behavioral

Be careful NOT everybody gives the same meaning
to the term BEHAVIORAL !
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RTL

• Only a small subset of the Language statements
  can be mapped in real Silicon.

area and timing constraints
generic technology
target technology
unoptimized generic boolean netlist
optimized gate level netlist
optimization mapping
translation
HDL code
SYNTHESIS
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Structural

• Sub-Modules interconnection
• Primitive cells interconnection (net-list)
• The code describes a bunch of port mappings.

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Behavioral

• Modeling a system (mimic functionality and
  performances)
• All language constructs can be used

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Levels of Abstraction
BehavioralRTLStructural
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VHDL Design Organization

• Entitythe symbol (input/output ports)
• Architectureone of the several possible
  implementation of the design
• Configurationbinding between the symbol and one
  of the many possible implementation. Can be used
  to express hierarchy.

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Entity
entity mux is port ( a in std_logic b in
std_logic s in std_logic f out std_logic
) end mux
MUX
A
B
F
S
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Architecture 1

• architecture first_rtl of mux is
• begin
• mux_p process (a,b,s)
• begin f lt (a and s) or (b and not s) end
  process mux_p
• end first_rtl

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Architecture 2

• architecture rtl of mux is
• begin
• mux_p process (a,b,s)
• begin if (s1) then f lt a
• else f lt b end if
• end process mux_p
• end rtl

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Configuration

• configuration mux_c of mux isfor rtlend for
• end mux_c

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Where did we get std_logic ?

• Ohps !! We need to include some library before we
  can use this predefined data type
• library ieeeuse ieee.std_logic_1164.alluse
  ieee.std_logic_arith.all

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Predefined data types

• bit 0 , 1
• boolean false, true
• integer from negative 231-1 to positive 231-1
• std_ulogic 1,0,H,L,X,U,Z,-,W
• std_logic 1,0,H,L,X,U,Z,-,W

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std_logic, and std_ulogic

• 1, 0, X ? logic 1, logic 0, unknown
• H, L, W ? weak 1, weak 0,
  weak unknown
• U, Z, - ? uninitialized, high
  impedance, dont care

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resolved or unresolved ?

• VHDL Driver it is one contributor to the final
  value of a signal
• Drivers are created by concurrent signal
  assignments
• Recommendation use std_logic, but always check
  that you do not have any multiple drivers (you
  dont want any wired OR inside an ASIC !!!)

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Bad Multiple Drivers!!!

• architecture bad of mux is
• begin
• -- the two assignment works in parallel
• f lt a when s 0 else 0
• f lt b when s 1 else 0
• end bad

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Better way of coding the mux

• architecture better of mux is
• begin
• f lt a when s 0 else
• f lt b when s 1 else
• X -- what should the synthesis tool do here
  ?
• end better

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One more coding for the mux

• architecture even_better of mux is
• begin
• f lt a when s 0 else
• f lt b when s 1 else
• - -- there are tools that wont appreciate
  all this -- freedom (e.g. some formal
  verification tool)
• end even_better

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Good way of coding the mux

• architecture good of mux is
• begin
• f lt a when s 0 else
• f lt b -- here all ambiguity are gone !!!
• end good

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What is a process ?

• A process statement is a concurrent statement,
  but all statements contained in it are sequential
  statement (statements that executes serially, one
  after the other).
• The use of processes makes your code more
  modular, more readable, and allows you to
  separate combinational logic from sequential
  logic.

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The sensitivity list

• List of all signals that the process is sensitive
  to. Sensitive means that a change in the value
  of these signals will cause the process to be
  invoked.

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The sensitivity list must be complete !!!

• process (a)
• variable a_or_b
• begin
• a_or_b a or b
• z lt a_or_b
• end process

-- since b is not in the -- sensitivity list,
when -- a change occurs on b -- the process is
not -- invoked, so the value -- of z is not
updated -- (still remembering the -- old value
of z)
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Incomplete sensitivity list effect
a
b
z
(VHDL)
z
(gate level)
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What to put in sensitivity list ?

• All signals you do a test on and all signals that
  are on the right side of an assignment.
• In other words all the signals you are reading
  in the value
• Dont read and write a signal at the same time
  !!!

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Object Types

• Constants
• Signals
• Variables

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Constant

• It is just a name for a value.reset_c 0
  bus_width_c 32- a better documented design.
  - it is easier to update the design.- But do
  not exaggerate !!! (since you have to remember
  all these names you defined)

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Signals

• It is a physical signal (you can think of it like
  a piece of wire)
• It is possible to define global signals (signals
  that can be shared among entities)
• But more often signals are just locally defined
  for a given architecture
• A signal assignment takes effect only after a
  certain delay (the smallest possible delay is
  called a delta time).

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Variables

• It is a used as a local storage mechanism,
  visible only inside a process
• All assignment to variables are scheduled
  immediately

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Signals vs. Variables

• Signals assignments are scheduled after a certain
  delay d
• Variables assignments happen immediately, there
  is no delay

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Delta Time

• architecture rtl of logic is
• signal a_or_b std_logic
• begin
• a_or_b lt a or b -- a_or_b is scheduled _at_
  tD
• z lt a_or_b and c -- z is scheduled _at_ t2D
• end rtl

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Bad example !!!

• architecture bad of logic is
• signal a_or_b std_logic
• begin
• logic_p process(a,b,c)
• begin
• a_or_b lt a or b
• z lt a_or_b and c
• end process
• end bad

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How to fix the bad example

• architecture good of logic is
• variable a_or_b std_logic
• begin
• logic_p process(a,b,c)
• begin
• a_or_b a or b
• z lt a_or_b and c
• end process
• end good

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Packages

• Packages offers a mechanism to globally define
  and share values, types, components, functions
  and procedures that are commonly used.
• package declaration and package body

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Subprograms

• Procedures can return more than one value (they
  can have both input and output parameters)
• Functions return always just one value (can have
  only input parameters)Example conversion
  functions, resolution functions,

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Attributes

• Info attached to VHDL objects
• Some predefined attributesleft ? the
  leftmost value of a typerighthigh ? the
  greatest value of a typelowlength ? the
  number of elements in an arrayevent ? a
  change on a signal or variablerange ? the
  range of the elements of an array object

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Generic

• parameter that pass information to an
  entityentity adder isgeneric (width integer
  5)port ( in_a std_logic_vector(width-1
  downto 0) in_b std_logic_vector(width-1
  downto 0) z std_logic_vector(width-1
  downto 0) carry std_logic))end entity
  adder

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Component (socket mechanism)

• Declare the name and interface of a sub-unit,
  to be used in the current level of design
  hierarchy.component addergeneric (width
  integer 5)port ( in_a, in_b in
  std_logic_vector z std_logic_vector carry
  std_logic)end component

adder
adder instance 1
adder instance 2
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Example a 7 bit adder (with bugs ?)

• adder-rtl.vhd

• big-adder-struct.vhd

a(30)
4 bits
b(30)
z(60)
a(64)
3 bits
b(64)
c
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adder-rtl.vhd

• --
• -- author Claudio Talarico
• -- file adder-rtl.vhd
• -- comment example of how to use generics and
  components
• --
• library ieee
• use ieee.std_logic_1164.all
• use ieee.std_logic_arith.all
• entity adder is
• generic (width integer 2)
• port ( a in std_logic_vector(width-1 downto
  0)
• b in std_logic_vector(width-1 downto
  0)
• c out std_logic --carry
• z out std_logic_vector(width-1 downto 0)
• )
• end adder

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big-adder-struct.vhd

• --
• -- author Claudio Talarico
• -- file big-adder-struct.vhd
• -- comment example of how to use generics and
  components
• --
• library ieee
• use ieee.std_logic_1164.all
• use ieee.std_logic_arith.all
• entity big_adder is
• port ( a in std_logic_vector(6 downto 0)
• b in std_logic_vector(6 downto 0)
• c out std_logic --carryout
• z out std_logic_vector(6 downto 0)
• )
• end big_adder
• architecture struct of big_adder is

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big-adder-struct.vhd

• -- CONTINUE FROM PREVIOUS PAGE
• begin
• inst_add_l adder -- low adder
• generic map (width gt 4) -- if there is
  more than one generic the separator is ,
• port map ( a gt a_in(3 downto 0),
• b gt b_in(3 downto 0),
• z gt z_out(3 downto 0),
• c gt c_l
• )
• inst_add_h adder -- high adder
• generic map (width gt 3) -- if there is
  more than one generic the separator is ,
• port map ( a gt a_in(6 downto 4),
• b gt b_in(6 downto 4),
• z gt z_out(4 downto 4),
• c gt c_h
• )

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ASSERT statement

• The ASSERT checks a boolean expression and if the
  value is true does nothing, else will output a
  text string to std output.It can have different
  severity levelsNOTE, WARNING, ERROR,
  FAILUREASSERT falseREPORT End of
  TestBenchSEVERITY ERROR

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COMPLEX TYPES

• enumerated typesTYPE color is (red, blue,
  yellow, green)
• ARRAYTYPE dbus is ARRAY (31 downto 0) of
  std_logic

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COMPLEX TYPES

• RECORDTYPE instruction isRECORD opcode
  integer src integer dest integerEND
  RECORD

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COMPLEX TYPES

• FILETYPE ram_data_file_t IS FILE OF
  INTEGERFILE ram_data_file ram_data_file_t IS
  IN /claudio/vhdl/tb/ram.txt

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More on FILEs

• use std.textio.all
• READ, WRITE, READLINE, WRITELINE, ENDFILE,

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Advanced Topics

• VHDL supports overloading