Review of Digital Logic Design Concepts

1
Review of Digital Logic Design Concepts
2
Basic Digital Logic Gates
3
Digital (Positive) Logic

• Logic Level High
• 1 or ONE or HIGH or H or Vdd or yes or ON or
  True
• Logic Level Low
• 0 or ZERO or LOW or L or GND or no or OFF or False

1
0
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Definitions

• Assert
• A control signal is asserted when the action
  control by the signal is being done.
• Ex Assume a control signal labeled en
• en is asserted when en is high
• Active low signal
• A signal that is asserted when it is a logic
  level low.
• Active high signal
• A signal that is asserted when it is a logic
  level high.

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Buffer
Equation
Symbol
Truth Table
A Y
0 0
1 1
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NOT (Inverter) GATE
Equation
Symbol
Truth Table
A Y
0 1
1 0
7
AND GATE
Equation
Symbol
Truth Table
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
8
NAND GATE
Equation
Symbol
Truth Table
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
9
OR GATE
Equation
Symbol
Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
10
NOR GATE
Equation
Symbol
Truth Table
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
11
XOR GATE
Equation
Symbol
Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
12
XNOR GATE
Equation
Symbol
Truth Table
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Equivalence Function
13
Digital Logic Types

• Combinatorial Logic Circuits
• No Memory (or Registers)
• Sequential Logic Circuits
• Memory (or Registers)
• Asynchronous Logic Circuits
• No common clock
• Synchronous Logic Circuits
• Common clock

Synchronous Sequential Circuits
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Memory Storage Registers

• Latches and Flip-Flops

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D-Latch with (P)reset
Symbol
d dont care
D E Pre Rst Qn1
d d 1 0 0
d d 0 1 1
d 0 1 1 Qn
0 1 1 1 0
1 1 1 1 1
Equation (level clock)
Truth Table

• When Pre/SET (Preset) is asserted, Q ? 1
  immediately.
• When Rst/CLR (Reset) is asserted, Q ? 0
  immediately.
• When neither SET nor CLR is asserted,
• Q ? D (data) when E (enable) is asserted
• Maintains previous value otherwise.

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D Flip-Flop Positive Edge Triggered
Symbol
D Clk Pre Rst Qn1
d d 1 0 0
d d 0 1 1
d 0 1 1 Qn
d 1 1 1 Qn
0 1 1 0
1 1 1 1
Equation (rising clock)
Truth Table

• Q changes to D on rising edge of Clk

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Finite State Machines
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Finite State Machines (FSMs)

• Three basic types
• Moore FSM
• Mealy FSM
• Mealy-Moore FSM

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Moore FSM General Block Diagram
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
CL Combinational Logic Cloud
Reg D Registers
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Moore FSM State Equations
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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Mealy FSM State Equations
Next State
Present State
Input Vector
Output Vector
Feedback Path
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Mealy-Moore FSM State Equations
Present State
Next State
Input Vector
Mealy Outputs
Moore Outputs
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State Diagrams
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State Bubble
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State Bubble Example
Unconditional Transition
State name S0 State value 00 Y 0 for this
state
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FSM Example
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Example 2 2-bit Up Counter

• State Diagram

Clock is implied
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Example 2-bit Up Counter

• State Table

State Value Assignment
S0 00
S1 01
S2 10
S3 11
Let
ps ns y
S0 S1 0
S1 S2 1
S2 S3 2
S3 S0 3
Output Vector
Let S0 reset state
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Example 2-bit Up Counter

• Truth Table

ps1 ps0 ns1 ns0 y1 y0
0 0 0 1 0 0
0 1 1 0 0 1
1 0 1 1 1 0
1 1 0 0 1 1
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Example 2-bit Up Counter

• Excitation Equations

31
Recall Moore FSM
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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Logic Diagram
No X Vector in this Example No H Logic needed
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2-bit Counter in 68HC11 Assembly

• L0 LDAA 00 Reset A with 0
• L1 INCA AA1
• CMPA 03 Is A3?
• BNE L1 No. Increment A
• JMP L0 Yes, Reset A to 0