Synthesizable High Level Hardware Descriptions

1
Synthesizable High Level Hardware Descriptions

• Jennifer Gillenwater, Gregory Malecha,
• Cherif Salama, Angela Yun Zhu, and
• Walid Taha
• Rice University
• Jim Grundy and John OLeary
• Intel Strategic CAD Labs

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The Designers Dilemma

• Hardware Description Languages (HDL) have useful
  abstractions
• Elaboration replaces abstractions with specific
  hardware descriptions
• Elaboration Preprocessing Expansion
• Currently, there are no tools to check
  synthesizability before elaboration
• Thus, designers avoid abstractions

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Can we Resolve this Dilemma?

• Statically verify synthesizability of a hardware
  description without having to elaborate it

4
HDL Constructs

• Structural Describe interconnections between
  hardware components
• Behavioral Describe circuit functionality at an
  algorithmic level
• Generate-like Describe the generation of more
  HDL code through elaboration

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Example Ripple Adder
module adder(s,cout,a,b,cin) input 30 a,b
input cin output 30 s output cout
wire 40 c assign c0
cin full_adder fa (s0,c1,a0,b0,c0) f
ull_adder fa (s1,c2,a1,b1,c1) full_add
er fa (s2,c3,a2,b2,c2) full_adder fa
(s3,c4,a3,b3,c3) assign cout
c4 endmodule
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Example Ripple Adder
module adder(s,cout,a,b,cin) input 30 a,b
input cin output 30 s output cout
wire 40 c genvar i assign c0
cin generate for(i0 ilt4 ii1)
full_adder fa (si,ci1,ai,bi,ci) endge
nerate assign cout c4 endmodule
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Example Ripple Adder
module adder(s,cout,a,b,cin) parameter
N4 input N-10 a,b input cin output
N-10 s output cout wire N0 c
genvar i assign c0 cin generate
for(i0 iltN ii1) full_adder fa
(si,ci1,ai,bi,ci) endgenerate
assign cout cN endmodule
Is this description synthesizable?
Can we determine that statically?
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Benefits of Static Synthesizability Check

• Saves time
• Designers can use high level abstractions
• We can check the synthesizability of families of
  circuits once
• No wasted time elaborating or synthesizing
  incorrect circuits
• Designers can use one language to describe
  circuits and circuit families
• Shows that properties of generated circuits can
  be checked before elaboration

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Outline

• Synthesizability
• Formalization of a core subset of Verilog
• Syntax
• Preprocessing semantics
• Type system
• Technical Results
• Prototype Implementation

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Synthesizability

• Obvious synthesizability

Directed Graph
Obviously synthesizable description
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Synthesizability

• Obvious synthesizability
• General synthesizability

Directed Graph
Obviously synthesizable description
Synthesizable description
Elaboration
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Synthesizability in Verilog

• From the previous definition,
• A Verilog structural description is obviously
  synthesizable if it is
• Syntactically correct
• Well-typed
• Abstraction free

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Formalization

• We use statically typed two-level languages
• Preprocessing is level 0 computation
• The result after preprocessing is level 1
  computation
• To do this we formally define
• Core syntax
• Preprocessing semantics
• Type system

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Featherweight Verilog (FV)

• Full Verilog is pretty complex
• FV includes the structural core of Verilog and
  supports the following abstractions
• Parameterized modules
• Generate blocks that might include loops and
  conditionals
• In FV, all constructs except abstractions are
  obviously synthesizable
• Defined in the paper using Backus-Naur Form (BNF)

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FV Preprocessing Semantics

• Defined using Big Step Operational Semantics
• Formalize elaboration
• Substitute parameters with their actual values
• Create a specialized module each time a module is
  instantiated with different parameter values
• Expand if constructs and for-loops
• Evaluate level 0 expressions
• Most interesting error is when level 0
  expressions depends on the value of a wire

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Preprocessing Example
module adder_4(s,cout,a,b,cin) input 30
a,b input cin output 30 s output
cout wire 40 c integer i assign c0
cin full_adder fa_0 (s0,c1,a0,b0,c0
) full_adder fa_1 (s1,c2,a1,b1,c1)
full_adder fa_2 (s2,c3,a2,b2,c2)
full_adder fa_3 (s3,c4,a3,b3,c3)
assign cout c4 endmodule
module adder(s,cout,a,b,cin) parameter N4
input N-10 a,b input cin output N-10
s output cout wire N0 c genvar i
assign c0 cin for(i0 iltN ii1)
full_adder fa (si,ci1,ai,bi,ci)
assign cout cN endmodule module main()
... adder (4) d1 (s1,cout1,a1,b1,cin1)
adder (2) d2 (s2,cout2,a2,b2,cin2)
... endmodule
module adder_2(s,cout,a,b,cin) ...
full_adder fa_4 (s0,c1,a0,b0,c0)
full_adder fa_5 (s1,c2,a1,b1,c1)
... endmodule
module main() ... adder_4 d1_0
(s1,cout1,a1,b1,cin1) adder_2 d2_0
(s2,cout2,a2,b2,cin2) ... endmodule
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FV Type System

• Defined as two-level typing rules
• Check signal types and directions
• Verify that expressions that need to be evaluated
  during preprocessing do not depend on wire values
• Leave out two conditions that are necessary to
  guarantee synthesizability
• Termination of for-loops
• Consistency of wire assignments (Each wire must
  be assigned exactly once)

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Technical Results

• We proved three theorems about FV type system
• Type Safety Preprocessing of a well-typed
  description does not produce an error
• Type Preservation Preprocessing of a well-typed
  description produces a well-typed description
• Preprocessing Soundness Preprocessing Produces a
  description that is free from abstractions
• Given that well-typed abstraction-free FV
  descriptions are obviously synthesizable, these
  theorems mean that our type system can statically
  guarantee the synthesizability of a program

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Prototype Implementation

• No preprocessing errors

Verilog Description (may contain abstractions)
ElaboratedVerilog Description
Type Checker(Typing rules)
Preprocessor(Semantics)
Well-Typed
Not Well-Typed

• Well-Typed
• Abstraction-Free
• Synthesizable

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How much can abstractions help in practice?

• Using abstractions, we manually re-factored some
  practical examples

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Conclusion

• We have defined obvious synthesizability and
  general synthesizability in a language and
  implementation independent way
• We have formalized syntax, semantics, and type
  system of a core subset of Verilog
• We formally proved key properties about our
  subset
• We showed that statically typed two-level
  languages can be used to check for
  synthesizability before elaboration
• Provided a prototype implementation demonstrating
  these concepts
• Our approach paves the way to provide other
  static guarantees about the hardware descriptions
• E.g. matching bus sizes, area, timing, and power