Test Generation and Optimization for DRAM Cell Defects Using Electrical Simulation

1
Test Generation and Optimization for DRAM
CellDefects Using Electrical Simulation

• Al-Ars, Z. van de Goor, A.J.Computer-Aided
  Design of Integrated Circuits and Systems, IEEE
  Transactions on , Volume 22 , Issue 10 , Oct.
  2003

2
Outline

• Introduction
• Conventional analysis
• Approximate Simulation
• New analysis
• Stress specification
• Test optimization
• Analysis results
• Conclusion

3
Introduction

• Electrical simulation has become a vital tool in
  the design process of memory devices
• The exponential complexity of the
  simulation-based fault analysis
• New methods to reduce the complexity of the fault
  analysis from exponential to constant
• Make it possible
• to use electrical simulation to generate test
  patterns
• to perform simulation-based stress optimization
  of tests

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Conventional Analysis
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Conventional Analysis

• 1O ? Rop ? 10M O
• 0v ? Vc ? Vdd (2.4v)

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Conventional Fault Analysis Result

• Conventional fault analysis result of open in
  Fig. 1 in the (Vc, Rop) analysis space

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Fault model

• Ref. Z. Al-Ars and A. J. van de Goor, Static and
  dynamic behavior of memory cell array opens and
  shorts in embedded DRAMs, in Proc. Design,
  Automation and Test Eur., 2001

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Fault Analysis Time (1/3)

• P is the number of points in the analysis space
• S is the number of operation sequence to be
  performed for each point
• Ts is the time needed to simulate each S

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Fault Analysis Time (2/3)

• X is the number of points taken along the x axis
  (Vc) of the analysis space
• Y is the number of points taken along the y axis
  (Rop) of the analysis space
• O is the number of operations (w or r) performed
  in S (ex. O3 for 1w0r0w1, O2 for 0w1r1)
• S typically starts with an initialization of
  either zero or one, followed by one of three
  possible memory operations w0, w1, or r for each
  increment in O
• T0 is the simulation time needed for a single
  memory operation

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Fault Analysis Time (3/3)

• X 10 points (0v ? Vc ? 2.4v)
• Y 15 ponts (1O ? Rop ? 10M O)
• S 18 (two-operation sequence)
• T0 10s of simulation time
• O 2
• Tpsim 54000s 15h

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New Analysis

• Approximate simulation
• reduce analysis time
• compromising the accuracy of the results
• Three different (Vc, Rop) result planes are
  generated
• successive w0
• successive w1
• successive r

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Result planes of the approximate simulation for
the operations (a) w0, (b)w1
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Result planes of the approximate simulation for
the operations (c) r

• Midpoint voltage (Vmp)
• Sense amplifier threshold voltage (Vsa)

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Approximating the Behavior

• Predict faults in any fault region of the
  conventional precise simulation
• Approximate the behavior resulting from any
  operation sequence performed on the defective
  memory
• Indicate the border resistance (BR)
• Generate a test that detects the faulty behavior

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Predict Faults
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Approximate the behavior resulting from any
operation sequence (1/2)

• 1w0w1r1 for Rop 100kO

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Approximate the behavior resulting from any
operation sequence (2/2)

• The memory behaves properly and no fault is
  detected using the sequence 1w0w1r1 for Rop
  100kO

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Indicate the border resistance (BR)

• BR is the resistive value of a defect at which
  the memory starts to show faulty behavior
• In this case, below the Rop value, the memory
  behaves properly for any possible operation
  sequence

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Indicate the border resistance (BR)

• Rop 200kO
• W1 operations can never result in detedting a
  fault

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Test generation

• When Rop ? 200kO, the sequence w1w1w0r0 can
  detect the fault

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Fault Analysis Time (1/2)

• P Y (because we do not take any point on the
  x axis)
• S 3 (w0,w1, and r)
• in order to keep a simulation accuracy along the
  x axis , we need at most X points along the
  axis, which means that we need at most O X

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Fault Analysis Time (2/2)

• X 4 (the average over the Rop range)
• Y 15 points
• S 3 (w0, w1,and r)
• To 10s of simulation time
• Tasim 1800s 0.5h
• Which is about 30 times faster than precise
  simulation
• Exponential speedup with respect to O

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Stress Specification

• Type of stress
• Voltage
• Timing
• Temperature

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Test Optimization

• A change in a given ST should modify the value of
  the border resistance in that direction which
  maximizes the resistance range that results in a
  detectable functional fault
• tcyc 60ns, T 27C , Vdd 2.4V and Rop 200kO
• By reducing the ability of 1w0 to write a low
  voltage into the cell
• By reducing the range of cell voltages in which r
  detects a zero

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Optimizing Timing
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Optimizing Temperature
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Optimizing Voltage
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Stress Combinations Evaluation

• Vdd 2.1V, tcyc 55ns and T 87C

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Stress Combinations Evaluation

• The used SC is very stressful, since (even with
  Rop 0O) a w0 operation cannot discharge Vc from
  Vdd to GND, and w1 cannot charge Vc up from GND
  to Vdd

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Analysis Results

• A real DRAM manufactured in 0.35-um technology

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Simulation Results
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Simulation Results

• Border resistance should decrease under stress
  for opens (Ot, Om, and Ob) and bridges (Bb and
  Bw)
• Border resistance should increase under stress
  for shorts (Sg and Sv)
• tcyc is by far the most effective ST

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Conclusion

• A new Spice-based test generation approach shown
  to provide a significant speedup in the analysis
  time
• The new analysis method reduces the analysis time
  by a factor of 30 compared to the conventional
  analysis
• A method to use defect simulation to optimize
  stresses for memory tests
• Stresses (timing, temperature, and voltage) are
  effective in bringing defective devices closer to
  failure