Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment

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Using Verilog VPI for Mixed Level Serial Fault
Simulation in a Test Generation Environment

• Pedram A. Riahi Zainalabedin Navabi
  Fabrizio Lombardi
• Electrical and Computer Engineering Department
• Northeastern University

ESA 2003
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Introduction

• System-on-Chip (SOC)
• SOC Testing
• Present Solutions
• Hardware Description Languages (HDLs)
• SOC Testing using VPI
• Case Study (PARWAN)
• Conclusion and Future Works

3
System-on-Chip (SOC)

• Complex Functional Blocks
• System-on-Board
• Core
• µP/µC
• DSP
• Memory
• Function-Specific
• Logic Element
• Communication
• Peripheral
• Analog Device

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System-on-Chip (SOC)

• Reusable Cores
• Core Types
• Soft (Synthesizable)
• Firm
• Hard
• Intellectual Property (IP)
• In-house cores

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SOC Testing

• Traditional Test Methods
• Core-Level Testing
• Design For Test (DFT)
• Automatic Test Pattern Generation (ATPG)
• Chip-Level Testing
• Justifying Test Sequences
• Propagating Test Response

6
Present Solutions

• Core-Level Testing
• System Chips Functional Test
• Direct Access (I/O Muxing)
• Local Boundary-Scan or Collar Register
• Full-Scan / Built-in-Self-Test (BIST)
• Proprietary Solution
• Chip-Level Testing

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Present Solutions

• Full-Scan / Boundary-Scan (FScan-BScan)

Full- or Partial-Isolating Rings / Control Points
FScan-BScan
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Present Solutions

• Full-Scan / Test Bus (FScan-TBus)
• Test Bus / Boundary-Scan Chain

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Present Solutions

• Binary Decision Diagram (BDD)
• Partial Netlist / Partial Boundary Scan

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Present Solutions

• Core Transparency

FPath
HScan
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Present Solutions

• IEEE P1500
• BIST
• Chip-Level Testing
• Parallel Direct Access
• Serial Scan Access
• Functional Access

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Hardware Description Languages (HDLs)

• VHDL
• Verilog
• Procedural Interfaces
• VHPI
• VPI
• Cadence Verilog-XL
• C Platform

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SOC Testing with VPI

• VPI-based
• Test Environment
• VPI-based
• Fault Simulation
• Single Stuck-at Fault
• Serial
• VPI-based
• Test Generation
• Random Pattern

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SOC Testing with VPI

• Mixed Level Fault Simulation

Wrapper Structure
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SOC Testing with VPI

• Proposed VPI Tasks for Fault Simulation
• faultlist
• Node Type reg, net
• Node Name .module_name/node_name
• Stuck-at sa0, sa1
• Not Injected
• Injected but not Detected
• Partially Detected
• Detected
• faultinjection
• updatefaultlist

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SOC Testing with VPI

• Proposed VPI Tasks for Test Generation
• faultcoverage
• morefault
• decide
• readstatus, restorestatus
• Status 0, 1, X, Z
• randomvector
• saveoutput, compareoutput
• savevector

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SOC Testing with VPI

• Initialization
• doread true
• faultlist
• while !(faultcoverage(coverage) satisfied)
• if (doread) readstatus
• randomvector(depth)
• readmem
• for (all vectors) Apply Vector saveoutput
• Fault Injection and Simulation
• Decide

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SOC Testing with VPI

• Fault Injection and Simulation
• Lindex 0
• while (morefault)
• restorestatus
• faultinjection(1)
• flag true
• for (all vectors and flag)
• Apply Vector
• if (compareoutput detected)
• updatefaultlistone(1)
• flag false Lindex Largest index
• faultinjection(2)

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SOC Testing with VPI

• Decide
• if (decide(limit) GOOD)
• savevector
• updatefaultlist(2)
• if (Lindex gt depth)
• restorestatus
• for (all vectors that index lt Lindex) Apply
  Vector
• doread true
• else
• restorestatus
• updatefaultlist(3)
• doread false

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Case Study (PARWAN)

• PARWAN
• Flat Serial Fault Simulation (WRTLT02)
• Mixed Level Module-based Serial Fault Simulation
• 45 Reduction in Simulation Run Time
• 12 Increase in Design Size

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Conclusion and Future Works

• A Test Methodology for SOC IP Core
• Mixed Level Module-based Fault Simulation
• and Test Generation
• ISCAS Benchmarks
• Serial Fault Simulation
• Linked-List instead of File (NATW03)
• Parallel or Deductive Fault Simulation
• Process-based Mixed-Level Fault Simulation
• Random Pattern Test Generation
• Reaching Higher Performance using VPI Built-in
  Features