Title: Silicon on Sapphire Test
1Silicon on Sapphire Test
- Wickham Chen
- 8-22-2005
- Southern Methodist University
2Purpose
- To provide test structures which will help
characterize the UTSI technology under high dose
of radiation. - Key points
- Is high performance and high radiation tolerance
possible in this technology? - How much radiation tolerance does this technology
have?
3Radiation effects
- Ionization creates electron hole pairs in a
semiconductor or insulating material - We know this as Total Dose effects.
- Creates defects mainly in the gate oxide and
oxide used for device isolation - In gate and substrate, pairs quickly disappear
due to little resistance. - In oxide,
- Within seconds a fraction of the radiation
induced electron hole pairs will recombine
immediately after being created. - Electrons are more mobile and typically swept out
of the oxide at high speed. - Ie. Positive bias on gate, electrons will drift
toward gate. - Holes however are less mobile.
- Some will recombine with electrons
- Usually a large amount are trapped inside the
oxide ie. Positive bias on gate holes travel
towards the Si02 and SI interface. - The positive charge holes are responsible for
changes in device properties. - Nuclear(atomic) Displacement
- Deals with Frenkel pairs (a vacancy-interstitial
pair formed when a atom is displaced from a
lattice site to an interstitial site ). In
silicon at room temperature 90 of Frenkel Pairs
recombine within a minute after end of the
irradiation. Limited importance according to
G.Anelli. - Neutrons are used to study displacement damage
(Neutron Fluence)
4Total Dose effects
- What are the key players?
- Change in threshold voltage.
- Increase in leakage current.
- Decrease of mobility.
5Total Dose effects
- When a MOS transistor is irradiated the threshold
voltage will change. - Change in ?Vt
- Given sum of ?Vox(related to hole trapping in
SiO2) and ?Vit(Charge state of the interface
traps).
6 ?Vox(related to hole trapping in SiO2)
- tox gate oxide thickness,Coxcapacitance per
unit area p(x) charge dist. In oxide per unit
volume as a function of the distance from the
gate oxide to interface x. - Observations
- Voltage shift is negative if you have positive
charge. - Closer the charge to interface the bigger the
threshold voltage shift.
7?Vit(Charge state of the interface traps).
- ?Qit is the difference of the charge per unit
area which fills the interface states after and
before irradiation.
8Increase in leakage current
- Edge leakage
- Creation of two parasitic paths under the a
region called birds beak - These parasitic paths are easily created since
the oxide in these regions are thick and thus
able to trap large amounts of holes.
9Increase in leakage current
- Back leakage current
- Trapped positive charge in the back channel
causing device failure. - Thick oxide acts as a parasitic transistor after
accumulating many positive charges.
10Decrease of Mobility
- Mobility decreases due to the increase of
interface trapping. - u0 pre-irradiation mobility. ?NitIncrease of
interface traps. Gammatechnology dependent
parameter.
11Single Event Effects
- (SEE) Single event effects are caused by a highly
energetic particle passing through an integrated
circuit. Usually this results in immediate
malfunctioning of certain transistors. - Can cause both reversible(soft) and
non-reversible errors(hard). - Types
- (SEL) Single Event Latchup(HARD)
- (SEU) Single Event Upset(SOFT)
- (SET) Single Event Transient(SOFT)
12Definition of SEL
- Single event latch up is the most destructive of
the single event effects.
13Definition of SEL
- Single Event Latchup (SEL) is a potentially
destructive condition involving parasitic circuit
elements forming a silicon controlled rectifier
(SCR). In traditional SEL, the device current
may destroy the device if not current limited and
removed "in time." A "microlatch" is a subset of
SEL where the device current remains below the
maximum specified for the device. A removal of
power to the device is required in all
non-catastrophic SEL conditions in order to
recover device operations.
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15SEL solutions
- SoS process. No silicon substrate so no SCR can
form.
16Single Event Upset
- SEU
- A reversible change in digital logic state due to
an energy particle passing through a device. It
is induced by the charges generated along the
track of the incoming particle which are
collected in the circuit sensitive node.
17Single Event Transient
- Current transient induced by a passing particle
can propagate through combinatorial logic and
cause an error.
18Single Event Upset and Transient Solutions
- Special concern in digital circuits
- These effects can be minimized through the
circuit design. - Can be eliminated by rewriting the information
lost.
19Layout countermeasures
- Enclosed layout
- Used by individuals at CERN
- Effective at suppressing edge leakage or birds
beak leakage. - Since such transistors laid out in this fashion
make sure that no overlap will ever occur between
field oxide and polysilicon and thus no channel
edge leakage.
20Enclosed Layout
21My modification
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23Proposed Floor Plan
(pads may vary)
- All units independent
- Large XY matrix (88) ofdevices to permit
statistical characterization - Nmos, pmos of different type
- All blocks have separateVDD and GND (so if
onefails, testing can continue) - For the XY matrix
- 10um, 1 finger 5um 2 fingers ELT
- For N and P
- 6 rows with different sizes
- 2 Differential pairs
Individual 5/6 transistors
Ring oscillators, small, big
Ring oscillators current mode
Transistor XY matrix
Shift registers
Shift registers
Individual gates
24Transistor XY matrix
GATE
25Specifics
- For individual transistors we will share the same
gate and have sources connected together (drain
individual for each column ). - During the test of the XY array(all the other
sources floated), add the same input to the gate,
add voltage at the output of the drain of
interest and measure the current. - Ring oscillator Gnd and Enable shared among the
2 rings. Vdd and output are individual. - May make four rings
- One standard cell with small size (To
characterize the parameter) - One standard cell with large size (5 times bigger
W, same L as the first one) - The same as above with ELT
- One with differential mode
26Specifics
- Inverter, Nand, Nor share the same inputs
- (2 input Nand, Nor)
- Common Gnd.
- Have individual Vdd and outputs.
- Total pads 21339 pads
- Gnd can be shared with the ring oscillators and
some other blocks. As long as we have individual
Vdd, we should be able to measure the current of
each block. - Shift register
- Input, clkc, output, Vdd, Gnd
- Zig-zag, square
- To connect resistors to every other latch.
27Layout methods
- How to distinguish leakage types
- Backchannel leakageproportional to width (W)
- Edge leakageproportional to fingers (M)
- These two layouts have different leakage
currents - Individual transistors (Devices), 10um
10
5
28Testing
- Bias N transistors with 2.5 V relative to
soruce,drain and body. - Bias P transistors with 2.5 V on the gate,source
and body relative to the drain. - Bias oscillators at 2.5V. (take 3 bias points at
3 voltages Vdd 1.25v, 2.5v, 3.5v) only change it
during testing. - Run shift register at around 100 mhz and use CMOS
buffer to drive pad. - Buffer With ELT layout, may or may not be
necessary
29Measurements
- Ids vs. gate voltage. For devices (single
transistors) - Leakage Current vs. Dose. For devices (Vgs0) and
gates - Measure Vdd individually all the blocks should
have individual vdd - Threshold Voltage shift vs Dose. For devices
- Delay vs. Dose, Power vs.Dose for oscillators.
For gates - Use a Hp4155 Semiconductor Parameter Analyzer to
measure Threshold voltage, transconductance and
subthreshold slopes? (or a custom test setup to
measure more quickly?) - Some type of efficient statistical analysis
software - Make spice models? (curve-fitting software
peregrine)
30BACKUP SLIDES
31Radiation
- Incident particle attacks a target material.
- What is important?
- For the incident particle
- Energy Involved?
- Mass and Charge?
- Type? Charged or Neutral.
- For the target material
- Atomic Number?
- Density?
32Incident Particles
- Charged Particles
- Attract or repelled by target atoms.
- Protons, heavy ions and electrons
- What can they do?
- Induce Ionization or atomic excitation.
- Nuclei interaction causing excitation or
displacement. - Electrons can observe scattering with the nuclei
which can cause their diplacement. - Nuclear reaction.
33Incident Particles
- Neutral Particles
- Neutrons and photons
- No Coulomb force
- Energy is important
34Incident Particles
- Neutron interaction
- Collisions
- Elastic continuation after collision with
nucleus. If energy is great enough the nucleus
can become displaced which in turn can cause
ionization or nuclear displacement. (slow and
fast) - Inelastic Similar to elastic but in addition the
nucleus is excited which then decays and releases
gamma rays.(Very high energies) - Nuclear reaction Neutron is absorbed by the
nucleus which then emits other particles(photons,g
amma,protons). Nuclear fission is acheivable.
(slow)
35Incident Particles
- Photon interaction
- Photoelectric effect-is the emission of electrons
from a surface (usually metallic) upon exposure
to, and absorption of, electromagnetic radiation - Photon ionizes atom and is absorbed. As the
photoelectric electron is emitted an electron in
an outer orbit of the atom will fall into the
spot vacated by the photoelectron, causing a low
energy photoelectric photon to be emitted. - Compton effect
- An electron of the target atom is set free and a
photon is emitted. - Creation of electron-positron pairs. Incident
photon annihilated.
36Incident Particles
- Effects of these incident particles can be
classified into Ionization effects and nuclear
displacement. - Caused by direct incident effects and also
secondary effects. - Nuclear Displacement Mainly caused by
neutrons(neutral and massive). - Ionization Effects Photons and Electrons
37SEL solutions
38(No Transcript)
39Proposed Floor Plan
(pads may vary)
- All units independent
- Large XY matrix (88) ofdevices to permit
statistical characterization - Nmos, pmos of different type
- All blocks have separateVDD and GND (so if
onefails, testing can continue) - For the XY matrix
- 10um, 1 finger 5um 2 fingers ELT
- For N and P
- 6 rows with different sizes
- 2 Differential pairs (7 pads Standard or ELT .
Buffer on these test structures ??? measure the
current of Ids, share the same pads on source,
gate, but different drain)
Individual 5/6 transistors
Ring oscillators, small, big
Ring oscillators current mode
Transistor XY matrix
Shift registers
Shift registers
Individual gates