Title: 12.4 MOS Transistor Matching
112.4 MOS Transistor Matching
- Analog Circuits use matched transistors ! Where
? - Differential pairs want voltage matching on VGS
- Current mirrors want current matching
- etc.
212.4 MOS Transistor Matching
MOS transistors can be optimized either for
voltage matching or for current matching, but
not for both !
gt Why ?
3- (1)Voltage matching
- Suppose two transistors, M1 and M2, operate at
equal drain currents. - Then, the possible voltage mismatch
- OFFSET Voltage DVGS DVt Vgst (Dk/2k2)
- To minimize DVGS
- use large W/L and low operating currents.
- minimize Vgst Vgst 0.1 volts or less.
4(2) Current matching The mismatch between ID1
and ID2 ID2/ID1 k2/k1 (1 2DVt/Vgst) DId
/ Id Dk/k 2DVt/Vgst ? To optimize ? use
reasonably large Vgst Vgst 0.3 V or more !
5So, Vgst 0.1 V or less for voltage matching and
Vgst 0.3 V or more for current
matching. Next is the effect of geometric
factors on the matching !
6- Geometric Effects on Matching.
- Increased Gate Area minimizes impact of local
fluctuations ? Large transistors match more
precisely. - Longer channels reduce linewidth variations and
channel length modulation ? Long-channel
transistors match more precisely. - Orientation of MOSFET matters.
- ? Gate Area, Oxide thickness, Channel length
modulation, Orientation,
7- (1)Gate Area
- Vt mismatch SVt standard deviation
- SVt CVt / (Weff Leff)1/2
- Where CVt constant.
- Only applies to carefully laid out MOS for
optimal matching. - Leff, Weff ? Ld, Wd if they are several times
greater than minimum.
8- (1)Gate Area
- k-mismatch Sk standard deviation in device
transconductance. - Sk / k Ck / (Weff Leff)1/2
- Where Ck constant.
- Linewidth variation
- Gate oxide roughness
- Statistical variation in mobility
9(2)Gate Oxide Thickness Scaling down to thinner
oxide ? seems to improve Vt-matching. ? not
affected is k-matching.
10- (3)Channel-length Modulation
- Short-channel MOSFETs ? severe mismatch in L if
different VDS ! - Mismatch DVDS / L
- Notes
- Ld 15-25 mm, adequate for noncritical use such
as current distribution network. - Matched transistors at similar VDS ?
Cascoding improves precision in matching.
11- (4) Orientation
- Several mismatch error
- Si wafer is under stress due to processing.
- The stress produces anisotropic effect on the
carrier mobility, etc. - Different orientation ? different stress effect
on the transconductance
- Stress-induced mobility variation ? several
- For example, tilted wafer ? as much as 5 in
matching errors.
12(4) Orientation
- Layout Editing
- Be careful with Cell editing when the matched
transistors belong in different cells ! - Group matched devices into the same cell
- May be more difficult to understand in the
Schematics - But safer for the matching !
13(4) Orientation
- Mirror-image layout vs. Superimposable layout
- Mask misalignment ? same effect on
superimposable but oppositie effect on
mirror-image. - So, be careful on asymmetric devices such as
Extended Drain MOS.
14- Diffusion and Etch effects on Matching
- (1) Effects of Poly Gate etching
- Consider the mask-step of defining Poly Gates
- Deposit Poly ? cover with oxide ? Mask pattern
for opening ?
remove Poly open region by etching - Etch rate depends on the size of Opening
- Larger opening ? faster etch.
15- Diffusion and Etch effects on Matching
- (1) Effects of Poly Gate etching
- Consider the mask-step of defining Poly Gates
- Deposit Poly ? cover with oxide ? Mask pattern
for opening ?
remove Poly open region by etching - Etch rate depends on the size of Opening
- Larger opening ? faster etch.
16Diffusion and Etch effects on Matching
- Dummy Gates need be electrically connected to
prevent spurious signal. - Best to connect Dummy Gates to the Backgate.
17- (3)Contacts over the Gate Poly
- Contacts in the active Gate region ? gross
variations in Vt ! - Gate contacts must be outside the active region,
on thick field-oxide. - Probably because of grain size, work function,
dopants, stress,
18- (3)Contacts over the Gate Poly
- Contacts in the active Gate region ? gross
variations in Vt ! - Gate contacts must be outside the active region,
on thick field-oxide. - Probably because of grain size, work function,
dopants, stress, - Annular MOSFETs ? particularly problem with gate
contatcs - Use Annular Transistors for Matched Devices only
if absolutely necessary. ? Make sure they use
identical arrangements, and minimal
number of small contacts.
19- (4) Diffusions near the Channel
- Deep Diffusions (e.g., deep-N sinker, Nwell, )
? diffusion tails extend much farther than
the junctions. - Spacing BETWEEN Matched Channels AND Deep
diffusion boundaries ? must be 2 times the
Junction Depth !
20- (4) Diffusions near the Channel
- Deep Diffusions (e.g., deep-N sinker, Nwell, )
? diffusion tails extend much farther than
the junctions. - Spacing BETWEEN Matched Channels AND Deep
diffusion boundaries ? must be 2 times the
Junction Depth ! - Spacing BETEEN Active Gate regions (of matched
transistor) AND the edge of the nearest NBL
region ? at least 150 of the epi
thickness.
21- Common-Centroid Layout of MOS Transistors
- Consider a MOS transistor with a couple of Gate
fingers. - Then consider matching two such transistors.
22- Common-Centroid Layout of MOS Transistors
- Consider a MOS transistor with a couple of Gate
fingers. - Then consider matching two such transistors.
23- Common-Centroid Layout of MOS Transistors
- Consider a MOS transistor with a couple of Gate
fingers. - Then consider matching two such transistors.
The MOS pair A B B A
24- Common-Centroid Layout of MOS Transistors
- Consider a MOS transistor with a couple of Gate
fingers. - Then consider matching two such transistors.
The MOS pair A B B A
Use S, D as subscripts ? DASBDBSAD
A
B
25Define Chirality of a Transistor Chirality
(the fraction of right-oriented segments)
(the fraction of left-oriented segements)
26Define Chirality of a Transistor Chirality
(the fraction of right-oriented segments)
(the fraction of left-oriented
segements) Examples) Three right-oriented and
One left-oriented segements ¾ - ¼ ½ Nine
right-oriented and Three left-oriented segements
9/12 3/12 ½ ? they can be matched
together w/o worry of orientation-dependent
mismatch.
27Example of Orientation-Dependent
Mismatch TILTED IMPLANTS
28Example of Orientation-Dependent
Mismatch TILTED IMPLANTS
Consider matching two transistors A and
B DASBD
29Rules of Common-Centroid Layout
1. Coincidence 2. Symmetry 3. Dispersion
4. Compactness 5. Orientation
30Rules of Common-Centroid Layout
1. Coincidence The centroids of the matched
devices must at least approximately
coincide 2. Symmetry The array should be
symmetric wrt both X- and Y-axes. 3.
Dispersion The segments of each device should
be distributed throughout the array as
uniformly as possible. 4. Compactness The array
should be as compact as possible. Ideally,
nearly square. 5. Orientation matched device
should possess equal Chirality.
31Simple Interdigitation Patterns for MOS
Transistor
1. (SADA)(SBDBSBDB)(SADA)S AB 11 2.
(DASBD-DBSAD)-(DASBD-DBSAD) 3. (DASBDBSA)D 4.
(SADASBDB)S(BDBSADAS) 5. (SADASBDBSADA)S
AB 21 6. (SADASBD-SADAS-DBSADA)S
AB 31 7. (SADASBDBSCDC)S(CDCSBDBSADAS) A
BC 111