Chapter 11, MOS Transistors

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Chapter 11, MOS Transistors
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• 11.1.1 Modeling the MOS Transistor
• (1) Effective Gate Voltage Vgst VGS Vt
• (2) ID VDS of NMOS
• Triode ( 0 lt VDS lt Vgst ) ID k (Vgst VDS/2)
  VDS
• Saturation (VDS gt Vgst )ID (k/2) Vgst2

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• Device Transconductancek k (W/L)
• Process Transconductancek m e0 er / tox
  set by process technology.
• Use mn 675 cm2/Vs, mp 240 cm2/Vs, e0
  8.85E-12 F/mNMOS kn 23000/tox mA/V2PMOS
  kp 8200/tox mA/V2
• Dielectric breakdown of oxide 0.1V/A ? limit
  Emax 30 mV/AMaximum possibleNMOS kn
  690/Vop mA/V2PMOS kp 240/Vop mA/V2
• ? Vop 5 volts gives 138 mA/V2 for NMOS,
  and 48 mA/V2 for PMOS.

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11.1.2 Parasitics of MOS Transistors
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11.1.2 Parasitics of MOS Transistors
NMOS in P-epi
N
P
NMOSCross-section
N
Equivalent Circuit
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11.1.2 Parasitics of MOS Transistors
NMOS in P-epi

• RG is minimized by siliciding Gate Poly (clad
  gate)
• RD, RS are minimized by siliciding the surfaces
  of S/D diffusions (clad moats).
• DDB, DSB are under reverse bias (if avalanche
  breakdown ? Zener), and mainly add Junction
  Capacitance to ckt.
• Q1 NPN Source-to-Backgate-to-Drain for a
  possible minority electron path. If they flow
  into adjacent wells, then CMOS latch up !

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PMOS in N-well
PMOS Xsection
P
P-epi
NWell
P
Psource-Nwell-Pepi
Equivalent Circuit
Pdrain-Nwell-Pepi
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• CMOS Latchup
• The positive feedback between the parasitic NPN
  of NMOS and parasitic PNP of PMOS leads to
  Circuit latchup.
• To prevent latchup, we need to block the minority
  carriers (that may be injected from forward NP
  of NMOS S-Backgate) from entering the
  Backgate of adjacent PMOS.

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CMOS Latchup
? PMoat guardring for PMOS, and Nmoat guardring
for NMOS.
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• 11.2.4 Threshold Adjust Implants
• Natural Transistor vs. Vt-adjusted Transistor
• Natural Adjusted Natural Adjusted
• Worst-case NMOS NMOS PMOS PMOS
• Minimum -0.10 0.50 -1.75 -1.15
• Nominal 0.20 0.80 -1.40 -0.80
• Maximum 0.55 1.15 -1.10 -0.50

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• 11.2.4 Threshold Adjust Implants
• Majority of analog processes offer Natural MOS
  transistors as part of the baseline process
  or as process extension.
• The Natural Vt mask is coded as NatVT.
• For example

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• 11.2.4 Scaling the Transistor
• ref Fund. Modern VLSI Devices, Taur Ning,
  Cambridge U.P., pp.
• The increasing level of integration on IC chips
  from 1973 (8 mm) to 2000 (0.2 mm) followed
  certain scaling rules.
• Constant-voltage scaling
• Constant-field scaling ? scale the device
  voltages and the device dimensions (both
  horizontal and vertical) by the same factor.

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11.2.4 Scaling the Transistor
CMOS VLSI Technology Generations Feature Supply
Gate Ox Ox Field Size(mm) Volt(V) Thickness(A)
(MV/cm) 2 5 350 1.4 1.2 5 250 2.0 0.8 5
180 2.8 0.5 3.3 120 2.8 0.35 3.3 100 3.
3 0.25 2.5 70 3.6
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For Length ? S x Length S lt 1 Parameter Const
ant- Constant- Voltage field Supply
voltage 1 S Size (tox, L, W,
xj) S S Doping(Na, Nd) 1/S2 1/S Field
1/S 1 Capacitance (CeA/t) S S Current
(I) 1/S S Gate delay (tCV/I) S2 S Power
dissip/gate(PVI) 1/S S2 Power-delay
product S2 S3 Circuit density
(1/A) 1/S2 1/S2 Power density (P/A) 1/S3 1
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• When migrating to newer processes, existing
  digital layouts are converted according to
  the scaling laws. For example,
• A program simply shrinks all data by the
  specified amount ? Optical Shrink.
• Follows either constant-voltage or
  constant-field law.
• Process engineers adjust tox and backgate doping.

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• 11.2.4 Variant Structures
• MOSFET rectangle of NMoat or PMoat, bisected
  by a strip of Poly
• OK IF W/L lt 10
• Not Convenient IF W/L gt 10
• Sectioned Transistors
• Large W/L ratio (e.g., gt 10)
• Multiple identical sections
• Ex) three-section transistor

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• Advantages
• More convenient aspect ratio
• Adjacent sections share S/D fingers ? reduced
  parasitics !
• Critical transistors must be laid out exactly as
  requested !
• Notation Sectioned Transistors
• N (W/L) N sections, each with drawn W/L ratio
• W/L usually means, it can have any number of
  segments desired
• But, if needs to match one having N(W/L)
  dimension, then must be laid out as a single
  section !

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• Merged Transistors
• When W is the same, then simple.
• When W is different, then SPM distance for
  Poly-to-Moat
• Example

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• Merged Transistors
• NAND example

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• Notes
• Analog cells can not use Autorouting software
  (thus no need for ports and prels).
• The height of analog cells is usually much
  greater than that of digital cells
• Larger component size
• Greater interconnection complexity

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• Serpentine Transistors
• A strip of NMoat or PMoat, covered by a plate of
  Poly.
• Channel length 2 LX LY W
• Dont match unless identical geometires.
• Example

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• Annular Transistors
• Square Gate or Circular gate

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• Annular Transistors
• CD limits speed for both digital analog.
  Miller Theorem !
• Smaller device ? smaller CD and smaller gm ! ?
  they offset each other.
• Must reduce CD/W
• Interdigitation reduces CD/W by half !
  ? two Gates surround one Drain !
• Annular Transistor ? smallest possible CD/W
  ratio because
  four Gates surround one Drain !
• The increased CS is usually OK because Source
  often connects to low impedance nodes.

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• Annular Transistors

• W 2 (C D)
• L (D-C)/2

• W p (B-A) / ln(B/A)
• L (B-A)/2

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• Elongated Annular transistor ?
  not recommended for minimizing CD !

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• Elongated Annular transistor ?
  not recommended for minimizing CD !

• Elongated circular annular transistor
• W p (B-A) / ln(B/A) 2 U
• L (B-A) / 2

• Elongated square annular transistor
• W 2V C D
• L (D-C)/2

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• Precision circuits ? always rely on
  matching between Identical devices !

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11.2.7. Backgate Contacts