P5 Evolution: Pentium MMX

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P5 Evolution Pentium MMX

• Pentium P5 with MMX Extensions
• Introduced 01/1997
• D-bus 64b. A-bus 32b
• Vcc 1.8V-2.8V
• 66-266MHz
• L1-caches 16kB code and data (write-back). 4-way
  set associative. More write buffers.
• 4.5M transistors. 0.25/0.35mm BiCMOS.
• 321-pin socket 7

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P5 Evolution Pentium MMX

• MMX
• MMX Multi-media ExtensionsTo meet growing
  importance and increasing demands of multi-media
  and communication applications
• 57 new instructionsNew instructions designed
  specifically to handle video and audio data
• SIMD Single Instruction Multiple DataOne
  instruction performs the same function on many
  pieces of data
• MMX is pipelined

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P5 Evolution Pentium MMX

• Main feature of multi-media applications
• an enormous number of small data packets must be
  processed, e.g. thousands of pixels required for
  a 3D object, or samples of music.
• SIMD Single instruction used for several data
  packets
• MMX implements a new register set of eight 64-bit
  registers
• MMX-registers shared with the 8 FPU registers
  80-bits width

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P5 Evolution Pentium MMX

• MMX data types
• Packed byte (8 Bytes)
• Packed word (4 Words)
• Packed double word (2 D-Words)
• Quad-word
• One instruction processes all 8/4/2/1 data units
  at the same time, e.g. addition
• Data units are treated as closed, i.e. no
  transfer between the individual data units
• SaturationValues in data unit will be clamped at
  pre-defined limits
• Example Video pixel with a color depths of eight
  bitsEight pixels can be packed together and
  processed in one go

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6th Gen. Processor P6

• P6 Processor Variations
• Pentium ProOriginal P6 processor. L2 cache
  256kB, 512kB or 1MB (full-core speed)
• Pentium IIP6 with L2-cache 512kB (half-core
  speed)
• Pentium II XeonP6 with L2-cache 512kB/1MB/2MB
  (full-core speed)
• CeleronP6 without L2 cache
• Celeron-AP6 with L2-cache 128kB on-die
  (full-core speed)
• Pentium IIIP6 with SSE (MMX2), L2-cache 256kB
  on-die (half-core speed)
• Pentium III XeonP6 with SSE (MMX2), L2-cache
  512kB/1MB/2MB on-die (full-core speed)

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P6 Main New Features...

• Dual Independent Bus (DIB)
• Two Separate Data Buses
• One system bus (motherboard)
• One cache busAlso called back-side bus to the
  processor
• Advantage Speed of the cache is scalable to the
  processor.In contrast P5 Cache-speed
  motherboard-speed. (thats why there is no P5
  processor gt 266MHz)
• P6 processors gt1GHz

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P6 Main New Features...

• Dynamic Execution
• Multiple Branch PredictionPredict the flow of
  the program through several branches. Goal Keep
  the instruction pipelines full.
• Dataflow analysisDetect opportunities for
  out-of-order instruction execution. Goal
  Optimise the use of the multiple superscalar
  execution units.
• Speculative executionExecution of instructions
  in advance of the actual program counter. Execute
  all available instructions in the instruction
  pool. Store the results in temporary registers.
  Retirement unit searches the instruction pool for
  completed instructions that are no longer data
  dependent on other instructions. If those
  instructions are found Results are committed in
  the order they were issued. Instruction are then
  retired from the pool.

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P6 Main New Features...

• Three-way superscalar
• P6 has at least six separate instruction units
• up to 3 instructions in one cycle

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P6 Main New Features...

• Other new features
• A few new instructions
• Enhanced multi-processor support
• Only recent Windows Versions (NT/2000/XP) do take
  full advantage of the P6s capabilities
• Use optimising compilers
• to make code as predictable as possible

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P6 Pentium Pro

• Introduced 11/1995(before P5 MMX)
• Outstanding featureIntegrated L2 cache
• Multi-chip module (MCM)Dual-cavity PGA
• 2 silicon diesProcessor L2 cache (256kB,
  512kB, 1MB)5.5M 63M 68M transistors
• Packaging extremely expensive !

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P6 Pentium II

• Introduced 05/1997
• Abandoned chip-in-a-socket
• Introduced 242-pin SEC cartridge
• Much less expensive to manufacture(at the time!)

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P6 Pentium II

• Processor core speeds 233-450MHz
• Bus speeds 66-100MHz
• 7.5M transistors. 0.25/0.35mm BiCMOS.
• MMX
• Power dissipation up to gt40W!Heatsinks and fans
  required!
• A-bus 36bAddressable 64GB
• L2 cacheHalf core-speed.Supports up to 512MB

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P6 Celeron

• Cheaper packaging (SEP)No fancy plastic
  cartridge
• Specifically designed for lower-cost PCs
• L2 cache support up to 4GB of RAM
• MMX
• L1 cache 2 16kB
• Integral thermal diode for temperature monitoring
• 0.25/0.18mm technology

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P6 Pentium III

• Introduced 02/1999
• 28M transistors
• 0.18mm coppermine technologyInterconnect Copper
  rather than Aluminium/Tungsten to reduce signal
  diffusion
• Major improvements
• SSE (Streaming SIMD Extensions)
• Integrated on-die L2 cache
• Available up to 1GHz

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7th Gen. Processor Pentium 4

• Introduced 11/2000. Also called NetBurst
• Main technical details
• Core speed range 1.3GHz..gt3GHz?
• 42M transistors. 0.18mm and 90nm
• System (front-side) bus up to 800MHz
• ALU runs at twice the processor core frequency
• Hyper-pipelined 20-stage technology
• Very deep out-of-order instruction execution
• 20kB L1 cache. 256kB full-speed L2-cache. 8-way
  set associative. L2 supports up to 4GB RAM and
  ECC.
• SSE2 144 new SSE2 instructions
• Socket 432. Up to 64W of power dissipation.

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Pentium 4 Latest News

• Pentium 4 Extreme Edition
• Main Features
• 90nm technology
• fclk3.73GHz
• FSB 1066MHz
• L2 2MB
• Socket LGA775
• Chipset 925XE Express

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Processors Review

• Processors are the brains of computers
• To fully understand present and future
  generations of processors it is vital to know
  their roots
• Weve covered Intel 16/32b processor generations
  (P1-P7) starting with 8086 (gt1978)

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Processors Review

• Weve covered Intel 16/32b processor generations
  P1-P7 focusing on
• Register set
• Bus interfacing. Read and write cycles. Wait
  states. Memory maps. Memory organisation.
• Modes of operation (real, protected, virtual)
• Segmentation. Paging. Logical, linear and
  physical addresses. Segment registers. Selectors.
  Descriptors and descriptor tables. Page
  directories and page tables. Segment protection
  and page protection.

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Processors Review

• continued
• Instruction pipelines and prefetch queues
• RISC versus CISC. Microcoding.
• Superscalar technology. Parallel pipelines.
  Instruction pairing. Branch prediction.
• Cache memories. Cache organisation. Hits and
  misses. Lines and sets. x-way set associative.
  Cache write strategies. LRU. Cache consistency
  and MESI states.
• Burst-mode bus cycles

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Outlook

• Remaining topics
• Memory components
• PC systems History and Evolution
• Legacy and state-of-the-art ports.Emphasis USB
• PC buses.Emphasis PCI
• Magnetic and optical storage devices