Todays agenda:

1
Todays agenda 1. the presentations for the
coming workshop.   20 min., Jingbo 2. status
report on the PCBs.                          10
min., Jingbo, Andy and Annie. 3. status report
on the PLL and the serializer design.  
30 min.   Ping, Peiqing and Junheng  
2
The workshop and SMU presentations, total 50
minutes. 1. SMU RD program overview.
10 min. R. Stroynowski 2. SoS
technology evaluation and LoC prototype 1 design
status. 25 min. P. Gui 2.1 Irradiation test
result on 0.5 um SoS laser driver chip. 2.2
design and fabrication of the 0.25 um SoS test
chip. 2.3 status of the LoC prototype 1
design block diagram, PLL details, ??? 3.
Irradiation test strategy, plan and
preparation. 15 min. J. Ye 3.1 test
strategy and plan on-line v.s.
before/after measurement. on-line
measurements signal generation error
detection,
current monitoring,
computer interface

gamma (TID) proton (TID SEE) neutron
(SEE)? Heavy ion (LET)? 3.2 preparation for
the SoS test chip and GOL irradiation tests in
May. 4. Discussion about the front end. 0 min.
should be pushed to Friday.
3
The PCB status The 4 boards (GOL, SOS carrier
boards, the Switch board and the FPGA board) have
been sent to Eagles. Intense interactions with
Eagles (including the past Sunday) take place to
make sure that we do not over look any mistakes
and lose any time here. This process will
continue for another week including the assembly
procedure, wire bonding procedure. The PCB fab
turn around is 10 days, assembly is 10 days, and
wire-bonding is 3 days. The 3 or 4 double layer
boards (the power board, the driver/fan-out
board, the TLK coupling board) design shall
begin Wednesday (tomorrow). We have about 20 days
to finish the design, layout and fabrication of
these boards. This puts us to mid April. What
need to be ready are the FPGA code and the
LabVIEW code. I understand that the LabVIEW code
is in good shape. The FPGA code needs intense
effort and care after April 5th, the date Wickham
has his qualifiers.