Transport Triggered Architectures

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Transport Triggered Architectures

• James Srinivasan
• Hardware Discussion Group
• Thursday 15th May 2003
• http//www.cl.cam.ac.uk/jrs53/

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Overview

• Introduction to the TTA concept
• Motivation and Challenges
• Examples
• Research Directions and Applications
• Feedback!

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Introduction

• Operation Triggered Architecture
• add r1 r2 r3
• Transport Triggered Architecture
• r1 -gt add
• r2 -gt add
• add -gt r3
• What about other kinds of instructions?

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Transforming Conditional Code

• Condition code registers
• Predicated moves
• cmp r1,r2 bne foo
• r1 -gt cmp
• r2 -gt cmp
• cmpneq -gt p
• foo -(p)-gt pc
• Similarly for squashing individual instructions

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Motivation

• Parallelism (ILP and more?)
• add r1 r2 r3
• r1 -gt add r2 -gt add
• add -gt r3
• Reduce register file traffic
• Functional units galore!
• Data movement under control of compiler
• Reduce power consumption
• Reduce access latency

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Challenges

• Need suitable compiler!
• Extract parallelism from HLL, perform static
  scheduling
• Need suitable interconnect!
• Ideally any-to-any but is this feasible?
• Low latency
• Is this the best use for silicon area?

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Examples

• MOVE32INT (TU Delft, 1993)
• 32 bit, 11 GPRs, 4 transports/cycle (64 bits)
• 2 integer units 1 logic unit 1 shift unit
• 1 immediate unit (?)
• 2 compare units
• 1 instruction fetch unit
• Sun FleetZERO (Sun Labs, 2000)
• Built to test async switch fabric

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Hardware Software Co-Design

• Designing software is easy, designing hardware
  isnt
• Application specific instruction set processor
• Automated design flow incorporates speed/area
  tradeoffs
• Specialised functional units
• At what level of granularity?

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Multi Threading and Virtualisation

• No binary compatibility
• So virtualise functionality and schedule at
  runtime
• Also supports execution of multiple threads in
  parallel
• Need hardware to produce conflict-free schedule
• Or could do in software
• Is this just OTA?

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Security

• Power analysis can compromise secure CPUs
• Keep all transports within a TTA busy
• Introduce dummy instructions
• Attacker cannot distinguish power used for real
  vs dummy code
• When is the best time to inject this code?

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Miscellaneous

• Compression of instruction stream
• I-stream rather sparse vs RISC
• Compress in software, decompress in hardware
• Unifying I/O
• Network processors
• Just another SFU?
• What about more distant communication?
• Single chip multiprocessor
• Multiprocessors
• Distributed multiprocessors

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References

• Microprocessor Architectures, from VLIW to TTA
• Henk Corporaal, Wiley 2002
• BYTE Overview Article
• http//www.byte.com/art/9502/sec13/art1.htm
• MOVE Project
• http//ce.et.tudelft.nl/MOVE/
• Sun FleetZero
• http//www.sunlabs.com/async/Publications/KeyPaper
  sPD1.html