A Hardware/Software Co-design Flow and IP Library Based on Simulink

1
A Hardware/Software Co-design Flow and IP Library
Based onSimulink

• L. M. Reyneri, F.Cucinotta, A. Serra, L.
  Lavagno
• June 21, 2001

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Introduction

• High-level design flow starting from SimulinkTM
• Allows application designers (not familiar with
  HW and embedded SW design) to quickly evaluate
  performance and cost impact of algorithmic and
  implementation choices
• Rich library of IP blocks
• Presentation outline
• Introduction to the supported co-design flow
• Tool feature description
• Models for performance estimation
• Example of application of this flow
• Conclusions and future works

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The co-design flow
Design and Functional Simulation
Prototyping board / System on a Chip
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Our contribution

• An implementation of this flow that relies on
• An enhancement to Mathworks SimulinkTM
• cost and performance analysis functions
• automated generation of VHDL and C glue code
• An in-house IP library parameterized by
• implementation choice (SW, HW, analog, digital,
  )
• bit width, architecture (serial, parallel,),
  pipelining
• where each block is equipped with a performance
  model, estimating
• chip area, code/data size
• latency in clock cycles
• energy per operation

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Types of IP Library Blocks

• The designer can select blocks from a large
  library including
• Low-level functions
• Addition
• Multiplication
• Min/Max
• Floating / fixed point converter
• High-level functions
• FIR filters
• Custom transfer functions
• Special-purpose functions
• Neural and Fuzzy evaluation blocks
• Interface blocks

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Functional Design in Simulink
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Main Extended Block Dialog Mask

• It contains
• Functional parameters (e.g. Integrator Gain)
• Implementation choice(e.g. HW, SW)
• Buttons to choose implementation-specific
  parameters(e.g. bit width and pipelining for HW)

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Digital HW Implementation Dialog Mask
It contains

• ImplementationArchitecture(serial, parallel)
• Pipelining level
• Output signal fixed point properties e.g. bit
  width, binary point, rounding mode,

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Structure of Digital HW blocks

• Data Conversion Cells (fixed point)
• Main Function cell (from our VHDL library)

A
Y
Converter
Converter
Main Functional Cell
Y_INT
A_INT
Z_INT
B_INT
B
Converter
Converter
Z
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Parameters and hierarchy
Look under symbol
All blocks contained in a hierarchical block
inherit the parameters set in its mask
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Monitor Block

• Must be added to the top level of each design
• Displays cost and performance analysis results
• Double-clicking on this block starts cost and
  performance analysis

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Cost and Performance Models

• The cost and performance models for each block
  are obtained

• for HARDWARE blocks, by curve fitting on a
  selected set of implementations for a
  representative combination of parameter values
• for SOFTWARE blocks, by worst-case execution time
  or power estimation

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Performance Analysis Algorithm

• Splitting of blocks according to their type
  (DigitalHW, SW, EXT)
• Computation of local performance information, by
  executing the Matlab performance model function
  associated with each block
• Computation of the global performance information
  and update of the results in the Monitor Block

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Example of Digital Hardware Cost
E.g., for a gain block (digital multiplier) if
(ispow2(gain)) area 0 just wiring elsearea
c1 c2 (nbit log2(gain)) c3 (nbit
log2(gain))2.
where c1, c2 and c3 depend on the chosen FPGA,
and are derived from several synthesis runs and
2nd order curve fitting.
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Digital Hardware Area (FPGA)
Area logic cells Ai area of the i-th
Digital Hardware Block n Number of Digital
Hardware Blocks
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Digital Hardware Energy (FPGA)
Energy nJ Ei energy of the i-th
Digital Hardware Block n Number of Digital
Hardware Blocks C Power Static Consumption
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Digital Hardware Latency
Latency Pipeline Stages/Clock Freq. latencyi
latency of the of the i-th Digital Hardware
Block P Set of all I/O paths in Digital
Hardware k Number of Digital Hardware Blocks
on path
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Application example
PID (Proportional Integral Derivative) control
for a MAXON brushless motor

• 3-phase, 12V, 40W
• 500 point per revolution incremental encoder
• driven by a 3-phase n-MOS bridge controlled by a
  PID controller

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Functional Design in Simulink
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Application example
Estimation accuracy for example
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Conclusions and future work

• Created a high-level design flow starting from
  SimulinkTM
• Allows application designers (not familiar with
  HW and embedded SW design) to quickly evaluate
  performance and cost impact of algorithmic and
  implementation choices
• Rich library of IP blocks (currently 25 blocks)
• Excel report file for the local performance
  figure
• Bounded dataflow protocol ensures functional
  correctness regardless of implementation choices
• Still to do
• automated insertion of HW/SW and A/D interface
  blocks
• integration of SW estimation tools
• automated partitioning