Combinational Logic Design

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Combinational Logic Design
digital systems are complex and sophisticated
Millions of gates
It is impossible to design each and every
implementation of functions from scratch.
Even seemingly simple expressions may turns out
to have not so simple implementations.
Fortunately, many expressions are compositions
of expressions we know and whose implementations
we can re-use and combine.
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Example 9 input Odd Parity Generator

• Design a circuit with nine inputs and one output
• if number of 1s in input is odd (even) then
  output is 1 (0)
• F(0, 0, 0, 0, 0, 0, 0, 1, 1) 0 F(1,
  0, 1, 0,1,0,0,0,0) 1
• What about the truth table? It has 29 512
  rows (!)
• 50 of these will have an odd number of 1s
• 256 minterms(!)
• It turns out that all minterms are
  prime!
• Conclusion 9x256 2304 literals!

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Parity generator and parity checker
Recall XOR function
X ? Y ? Z ?m(1, 2, 4, 7)
Such functions are special. They are called Odd
Functions. Why?
Parity Generator P X ? Y ? Z Parity Checker
C X ? Y ? Z ? P
MESSAGE (X,Y,Z,P) Total number of 1s even
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Example 9 input Odd Parity Generator (contd)

• XOR(X,Y) computes odd parity
  of two inputs (X, Y)
• XOR(XOR(X, Y), Z) computes odd parity of
  three inputs (X,Y,Z)
• Thus, odd parity of 9 inputs is
  generated by

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Combinational Logic Design
How to design combinational circuits?
Use fundamental circuits called basic
blocks Re-use basic blocks to design new
circuits Use hierarchy Use tools for Computer
Aided Design
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Example The 9-variable PG
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Computer-Aided Design

• Schematic capture tools
• Graphical editors to support drawing and
  interconnecting
• of blocks at all levels of the hierarchy.
• Libraries
• Provide lots of graphics symbols from gates to
  basic
• blocks and more.
• Logic Simulators
• To evaluate and validate the functional behavior
  and
• timing behavior of your design.
• Logic Synthesizers
• To optimize the design for minimum area,
  delay, and
• power in the realization.

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Hardware Description Languages

• HDL is a programming language used to describe
  hardware behavior and structure (structural
  description).
• It can deal with parallelism. It is a powerful
  alternative to schematics.
• Two standards VHDL and Verilog

Unfortunately, I can not teach you this
language(s) because of lack of time.
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Analysis is circuit behaving well?

• A circuit is designed to inplement a function.
• Question is the design correct?
• Answer find the circuits actual input-ouput
  relation and see
• whether it is the desired
  function.
• How?
• 1. Label gate outputs that depend on input
  variables directly
• 2. Write Boolean functions for these gate outputs
• 3. Repeat process until final output is obtained

Alternatively build up Truth Table instead of
function.
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Finding the circuits function
T1B'C T2A'B
B'D
T3T1AAB'C
F2 T5 A'B D

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Truth Table from Circuit

• Write input rows (2n, where n is the number of
  inputs)
• 2. Break circuit up into blocks, label each block
  with symbol
• 3. Obtain truth table for blocks with functions
  that depend on input variables only
• 4. Go on to obtain truth table for blocks with
  functions that
• depend on previously defined inputs and
  block outputs,
• until columns for all circuit outputs are
  found.

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Example Circuit to Truth Table
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Circuit to Truth Table (contd)
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Lets Design Circuits

• We know by now how to do, dont we?
• 1. Define inputs and outputs to circuit, specify
  names
• 2. Derive truth table that defines the required
  relationship
• between inputs and outputs
• 3. Obtain simplified Boolean expressions for
  output functions
• 4. Draw logic diagrams.
• 5. Check correctness of the design.
• Example 3-1 on page 106 is a simple
  illustration
• ( read it!)

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Code Convertors
Code converters translate a particular binary
code to another.
Frequently used converters are
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Decoders

• Recall, A decoder is a circuit that has n inputs
  and m ? 2n outputs
• Terminology 2-to-4 line decoder,
  3-to-8 line decoder,
• Outputs are minterms (or maxterms) of the
  inputs
• Example 2-input decoder. Inputs A1, A0.
  Outputs D3, D2, D1, D0

m0
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Decoder is basic block

• Again, decoders are basic blocks. We use them
  over and over
• again as we shall see.

Youll find this symbol in library
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Design
enable bit instructs decoder when it is to be
active all outputs are zero if
enable bit is zero
Truth Table
Example D0 (A0 A1 E')' A0 ' A1 '
E m0E
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Full adder with decoder

• As we know, the full adder has
• Three inputs two bits to be added and a carry-in
• Two outputs sum and carry out
• Logic Functions
• S(X, Y, Z) ?m(1,2,4,7)
• C(X, Y, Z) ?m(3,5,6,7)
• Idea Decoder offers all
• minterms. So
• OR minterms in S
• and C from decoder.

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Bigger decoders from small once

• Given 2-to-4 decoders
• Required 3-to-8 decoder
• Solution each decoder realizes half the
  minterms. Enable selects which decoder is active

A2 0 enable top decoder A2 1 enable bottom
decoder
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Encoders

• Recall encoder is inverse operation of decoder.
  From minterms to binary
• It has 2n inputs Dk, and n outputs
  Al.
• the n outputs form together the binary code of
  the one input that is 1

Consider a base-4 number (B3B2B1B0)4. To convert
to binary, start with B0. If B0 N (0, 1, 2 or
3), set DN to 1 and all other Dk to zero.
Output is binary N.
D2 1
What should happen when two inputs are 1?
Undefined!
Not very useful
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Priority Encoder
This is a condensed truth table corresponding to
16-row table. If you understand it, then you
really understand dont cares
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Multiplexer
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4-to-1 Multiplexer
"Truth Table"
select enable output
Actual truth table has 27 128 rows
D0, ,D3 S0, S1 and E
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4x1 MUX
The four underlined terms remind me of a decoder!
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2-input bit bus
A bus is a communication path to which several
units have access, not at the same time. An
arbiter is regulating the traffic. If two data
words ASK for the bus, only one get it.
All A (S0) or all B (S1)
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4x1 MUX from 2x1 MUX'es
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Implementing functions with MUX
We already used decoders to implement functions.
A MUX is essentially a decoder (with the muxs
external OR gate absorbed).
Lets
implement F(X,Y,Z) ?m(1,2,6,7) .
X Y Z F 0 0 0 0 0 0 1 1 0
1 0 1 0 1 1 0 1 0 0 0 1 0 1
0 1 1 0 1 1 1 1 1
F is either Z, or Z, or 0, or 1 and (X,Y)
is uniquely determining which one of these.
So, take X and Y as the 2(!) selection bits, and
Z, Z,0 and 1 as the 4 corresponding data bits.
X S1, Y S0, Z D0, Z D1, 0 D2, 1 D3, F
Out
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The Demultiplexer
Recall a demultiplexer performs the inverse
function of the MUX.
D0 (S0 S1 D')' S0 ' S1 ' D m0D
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Programmable Logic
In general, Programmable Logic Array (PLA)
consist of two arrays
An AND array, and An OR array.
Array logic
Two-input AND
OR array
AND array
Three-input OR
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Types

• AND array is fixed (decoder), OR array is
• programmable
• AND array is programmable, OR array is fixed
• 3. AND array and OR array are programmable

The names programmable logic devices
2. Programmable array logic (PAL) devices
3. Programmable logic array (PLA) devices
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Read-only Memory (ROM)
Address in
Data out
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ROM design
Is a Truth table
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Progable Logic Array (PAL)
In a PLA, the decoder of the PROM is replaced by
an AND array.
The AND array has the same function as the
decoder generating product terms.
k P-terms (four)
PLA Programming table.
n inputs (three)
When programmable by user, PLA is called field
programmble.
m outputs (two)
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Progable Array Logic (PAL)
In these programmable devices, the OR array is
fixed.
PALs are composed of a number of PAL sections.
Out
Each section consists of
In
Product terms cannot be shared among sections.
Thus each output (function) can be simplified by
itself (unlike in PALs where you want to share
product terms).
The number of P-terms in a section is fixed. If
you need more, use more sections.
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Example.
PAL Programming Table.
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FPGAs
Most popular are Xilinx and Altera. See
your hands-on exercise implementations.
Ill come back to them when we have
seen sequential circuits.
Programming FPGAs is all you have to master to
realize even very complicated digital systems
Thats exactly what you will master by the end of
the course.
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Summary
Learned how to design combinational circuits
Learned how to analyse combinational circuits
Defined, designed and used important basic blocks
called code Converters
n
Decoder almost always with enable bit.
Generates m ? 2
min (max) terms of the n variables input to it.
n-to-m line decoder
n
Multiplexer takes data from one of 2
single-bit lines selected
through an n-bit input selection code.
n
2 -to-1 line multiplexer
essentially a decoder an many-input OR gate
Demux inverse MUX. Structurally identical to
Decoder .
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Recall XOR is not a basic gate. We write F X ?
Y and the meaning is F is 1 if and only if X1
or Y1 but not both.
It is a shorthand for the following
Does it work?
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Managing Complexity

• Hierarchical Design
• A system consists of subsystems.
• Subsystems consist of units or blocks, units
  consist of subunits,
• Top-down design
• Partition a system into subsystems, subsystems
  into units, .
• When well done, the whole system is decomposed
  into basic blocks
• that you have to design (or someone else has
  already done library)
• Composition
• Interconnect basic blocks, subunits, units,
  subsystems correctly to
• get the system design.
• Use tools (computer) to assist you

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Example BCD to Seven Segment Code Converter
Input is BCD-code Need four variables A, B, C,
DOutputs are seven functions to drive LED
segments a-g example A0, B1, C0, D1
denotes "5 convert (ABCD) 0101 to
(abcdefg) 1011011
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Truth Tables
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Synthesize Function 'a'
EPI's A'C, AAB'C'. Other PI's B'C'D',
A'BD
C
B
A
D
Map for function 'a'
a A'CA'BDAB'C'B'C'D'
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Verify Boolean Expression for 'a'