VMEbus

1
VMEbus

• Outline
• Introduction
• Electrical Characteristics
• Mechanics
• Functions
• Data Transfer
• Arbitration
• Priority Interrupt Bus
• Utilities
• Goal
• Understand VMEbus fundamentals
• Reading
• Microprocessor Systems Design, Clements, Ch. 10.3

2
Introduction

• VERSAbus -gt Versa Module Europe bus -gt VMEbus
• developed for Eurocard in 1981 - popular PC card
  format
• originally Motorola bus, now ANSI/IEEE/IEC
  standard
• Objectives
• allow two cards to communicate independent of
  other cards
• electrical and mechanical specification
• protocol specification
• terminology and definitions to precisely describe
  protocols
• allow broad design latitute for cost/performance
  optimization
• 8, 16, 32-bit data widths, 24, 32-bit address
  widths
• performance is device limited, rather than
  interface limited

3
Electrical Characteristics

• TTL compatible
• standard TTL voltage levels
• simple interfacing
• Bus size
• 21 slots across 500 mm
• permits high speed
• Protection
• inputs clamp negative excursions at -1.5V
• TTL gates do this already
• maximum driver short-circuit current specified
• Drive capability
• AS, DS0, DS1 must have high current drive
• bus arb, IACK can have low drive
• 330/470 ohm signal termination (equiv to 2.49V
  into 194 ohms)
• can be used for open collector
• floating lines go high

4
Mechanics

• Specifies single or double height cards
• 132.5 mm or 265.9 mm slots
• 100 mm by 160 mm or 233.35 mm by 160 mm boards
• Two connector system
• 96-pin connectors
• primary connector P1 - provides all VMEbus
  functions
• used on single-height cards
• 24-bit address, 16-bit data buses
• secondary connector P2
• on double-height cards
• use for 32-bit addresses, 32-bit data bus

5
Functions

• VMEbus is logically 4 separate buses
• cards only need to implement parts they need
• Data transfer bus (DTB)
• data, address, control lines for master to slave
  communication
• DTB arbitration bus
• determines who will be DTB master
• Priority interrupt bus
• 7 level interrupts
• Utility bus
• clock, reset, system fail, A/C fail lines

6
Bus Functional Modules

• DTB requestor
• on board with master or interrupt handler
• can request control of bus
• Interrupter
• can generate interrupt request for master
• can provide status information to interrupt
  handler on request
• Interrupt handler
• can detect and handle interrupt requests
• DTB arbiter
• receives DTB arbitration requests, prioritizes
  them, and grants bus to requestor
• DTB slave
• responds to data transfer requests by master
  (e.g. memory)
• DTB master
• can initiate bus transfers (e.g. CPU, DMA)

7
Data Transfer Bus

• Extension of 68000 asynchronous bus
• but signals latched on clock
• UDS/LDS -gt DS1/DS0
• LWORD - 32-bit transfer
• AM0-AM5 - address modifier
• pass extra information to slave, e.g. FC0-FC2
  from 68000
• memory map manipulation, address range
• privilege levels
• Transfers
• 1-256 bytes at at time
• address-only cycle
• separate address and data strobes so master can
  send next address before it reads data

8
Arbitration

• Arbiter
• in slot 1, determines master among requestors
• BR0-BR3 - bus request priority lines
• arbiter can operate in round robin of priority
• arbiter can grant to highest priority
• single level priority - BR3 only
• daisy chain modules so highest priority are
  closer to arbiter
• Signals
• BGxOUT - bus grant outputs
• BGxIN - bus grant inputs
• used to daisy chain priority lines
• BBSY - busy, asserted by new master
• BCLR - clear, asserted by arbiter - give up bus

9
Priority Interrupt Bus

• 7-level prioritized vectored interrupts
• use D0-D7 for interrupt ID
• Can have more than one interrupt handler device
• Signals
• IRQ1-IRQ7
• IACK
• IACKIN - daisy chain in
• IACKOUT - daisy chain out
• makes sure only one interrupter gets
  acknowledgement
• pass signal if not the requester at that
  interrupt level using interrupt acknowledge level
  on address bus

10
Utilities

• SYSCLK - system clock, 16 MHz
• freerunning, no phase relationship to other
  clocks
• can use for local clock generation
• SYSRESET - system reset
• open collector, from reset button, power monitor,
  etc.
• SYSFAIL - system failure
• cards keep low until they have powered up
• assert when card detects failure
• ACFAIL - A/C power supply has failed
• cards can do power-down sequence