Exam Examples

1
Exam Examples

• Kleitz Chapters 10 and 12

2
Example 10-3
G S R Q
3
7475 D Flip Flop Timing Example
G D D Q
4
7475 D Flip Flop Timing Example
G D D Q
Gate is high and D high so reset initially. Then
D sets high. No change when clock is low.
5
7475 D Flip Flop Timing Example
G D D Q
Reset, then set during clock pulse. No change
when clock is low.
6
7474 D Flip Flop Timing Example (Asynchronous
Inputs Held High)
G D D Q
hold
set
reset
reset
7
7475 D Flip Flop Timing Example Problem 10-10
G D Q
Q follows D when enable is on. Otherwise Q
remains where it was.
8
7474 D Flip Flop Timing Example Problem 10-16
Q D at positive gate edge.
G SD RD D Q
AS
AR
AR
SR
SS
SS
9
Example 10-15 7474

• from overhead

10
Homework 10-26

• 7476 is J-K Pulse triggered master-slave
  flip-flop
• Master output reflects all changes during clock
  pulse.
• State of master J-K at end of pulse will transfer
  to slave Q when pulse goes low.

11
Homework 10-26 Sketch Q for 7476
G S R J K Q
12
Homework 10-26

• 74LS76 is J-K negative edge triggered flip-flop
• State of J-K at falling edge of pulse will
  transfer to Q.

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Homework 10-26 Sketch Q for 74LS76
G S R J K Q
Toggle Hold Hold Toggle
14
Homework 10-28 Sketch Q for 74LS76
Cp S R J K Q
ST
AR
ST
ST
ST
Resets then toggles at 1/2 frequency.
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Homework 10-40

• See Electronic Workbench solution
• 10_1bsolve.ewb

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Homework

• Due Monday 11-22
• Late homework will not be accepted.
• End of Chapter 12, page 462-464
• 12-6, 12-8, 12-16
• multiple choice or short answer
• 12-18, 12-28
• design problem

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Example 12-4

• from overhead

18
Example 12-7 e

• How many J-K flip flops to make a MOD-33
  counter?
• will count 0-32 reset on 33.
• takes six. 25 32
• 33 100001. Six bits to reset.

19
Example Problem 12-27

• Assume you have one 7490 and one 7492. Show the
  external connections required to form a divide by
  24.

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Recall 7490

• 7490.
• Divide by 2.
• Divide by 5.

21
Recall 7492

• Divide by 2
• Divide by 6

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Solution

• Use 7490 to
• divide by 2
• Use 7492 to
• divide by 2 and divide by 6
• Result is divide by 2 x 2 x 6 24

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Connections 7490

• Connect Vcc and ground pins
• MR1, MR2, MS1, MS2 to ground
• defeats asynchronous set/reset
• Cp1 is not used
• connect to low to prevent problems
• Q1, Q2, Q3 not used
• External clock to Cp0
• Q0 of 7490 to Cp0 of 7492

24
Connections 7492

• Connect Vcc and ground pins
• MR1, MR2 to ground
• defeats asynchronous reset
• Cp0 connected to 7490 Q0
• Cp1 connected to 7492 Q0
• Q3 is the desired output.

25
Example 12-13

• Goal use 7490 for a MOD-8 counter.
• Counts from 0 to 7 and resets on 8.
• And when turned on, counter is set at 9.
• First negative clock edge will set count to 0.

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Example 12-13

• See 7490 pin-out inside front cover.
• Must output 9 (1001) which requires 4 bits
• Need both divide by 2 section and divide by 5
  section.
• Tie Q0 to Cp1

27
Example 12-13

• MOD-8
• reset at 8 (1000) after 7 (0111)
• thus reset when S31
• however 9 (1001) is the power up state. Do not
  reset on 9.
• so reset on S31 AND S00

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Example 12-13

• Set to 9 on power up.
• Need 1s to both Master Sets.
• Use series R-C circuit.
• voltage across capacitor to MS1,2
• capacitor initially discharged
• voltage across it is zero (logic low)
• capacitor charges to logic high
• Problem capacitor rise time is slow.
• Desire fast and certain transition.

29
Schmitt Trigger

• Chapter 11 topic skipped
• For us
• This is an electronic circuit which takes a
  noisy or slow signal and converts it to a clean
  square wave.
• Examples

30
Application 12-3 Counter

• Goal count from 0 to 999 in decimal.
• First recall 0 to 9 counter.
• 7490
• Decade counter MOD-10
• Gives BCD output
• Clock input is negative edge triggered.
• Output will count to 9 (1001) then next count
  will be 0 (0000).
• MSB transitioned from 1 to 0

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Application 12-3 Counter

• MSB high to low gives falling edge for input to
  next 0-9 counter.
• Second counter increments by 1.
• Each 7490 provides BCD output for one power of
  ten.

32
Application 12-3 Counter

• Connections
• Master Resets to ground to defeat.
• Master Sets to ground to defeat.
• Tie each ICs Q0 to Cp1 so divide by 2 section
  is tied to divide by 5 section.
• Tie MSB of LSD (least significant digit) to Cp0
  of middle decade counter.
• Tie MSB of middle to Cp0 of MSD.